R5F21346CNFP#U0 Renesas Electronics America, R5F21346CNFP#U0 Datasheet - Page 346

• Manufacturer Part Number: R5F21346CNFP#U0
• Description: MCU 1KB FLASH 32K ROM 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/34Cr

Specifications of R5F21346CNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 43
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/34C Group
REJ09B0586-0100 Rev.1.00 Jan 13, 2010
Page 313 of 723
Table 20.5
i = 0 or 1, j = A, B, C, or D
Count sources
Count operations
Count period
Count start condition
Count stop condition
Interrupt request generation
timing
TRDIOA0 pin function
TRDIOB0, TRDIOC0,
TRDIOD0, TRDIOA1 to
TRDIOD1 pin functions
INT0 pin function
Read from timer
Write to timer
Selectable functions
Item
Input Capture Function Specifications
f1, f2, f4, f8, f32, fC2, fOCO40M, fOCO-F
External signal input to the TRDCLK pin (valid edge selected by a
program)
Increment
When bits CCLR2 to CCLR0 in the TRDCRi register are set to 000b
(free-running operation).
1/fk × 65536 fk: Frequency of count source
1 (count starts) is written to the TSTARTi bit in the TRDSTR register.
0 (count stops) is written to the TSTARTi bit in the TRDSTR register
when the CSELi bit in the TRDSTR register is set to 1.
• Input capture (valid edge of TRDIOji input or fOCO128 signal edge)
• TRDi register overflows
Programmable I/O port, input-capture input, or TRDCLK (external clock)
input
Programmable I/O port, or input-capture input (selectable by pin)
Programmable I/O port or INT0 interrupt input
The count value can be read by reading the TRDi register.
• When the SYNC bit in the TRDMR register is set to 0 (timer RD0 and
• When the SYNC bit in the TRDMR register is set to 1 (timer RD0 and
• Input-capture input pin selection
• Input-capture input valid edge selection
• Timing for setting the TRDi register to 0000h
• Buffer operation (Refer to 20.2.2 Buffer Operation. )
• Synchronous operation (Refer to 20.2.3 Synchronous Operation. )
• Digital filter
• Input-capture trigger selection
timer RD1 operate independently).
Data can be written to the TRDi register.
timer RD1 operate synchronously).
Data can be written to both the TRD0 and TRD1 registers by writing to
the TRDi register.
Either 1 pin or multiple pins among TRDIOAi, TRDIOBi, TRDIOCi, or
TRDIODi.
The rising edge, falling edge, or both the rising and falling edges
At overflow or input capture
The TRDIOji input is sampled, and when the sampled input level match
as 3 times, the level is determined.
fOCO128 can be selected for input-capture trigger input of the
TRDGRA0 register.
Specification
20. Timer RD