R5F21346CNFP#U0 Renesas Electronics America, R5F21346CNFP#U0 Datasheet - Page 376

• Manufacturer Part Number: R5F21346CNFP#U0
• Description: MCU 1KB FLASH 32K ROM 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/34Cr

Specifications of R5F21346CNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 43
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/34C Group
REJ09B0586-0100 Rev.1.00 Jan 13, 2010
Page 343 of 723
Figure 20.11
20.4.20 Operating Example
The above applies under the following conditions:
The CSELi bit in the TRDSTR register is set to 1 (the TRDi register is not stopped by compare match).
Bits BFCi and BFDi in the TRDMR register are set to 0 (registers TRDGRCi and TRDGRDi are not used as buffer registers).
Bits EAi, EBi, and ECi in the TRDOER1 register are set to 0 (enable the TRDIOAi, TRDIOBi and TRDIOCi pin outputs).
Bits CCLR2 to CCLR0 in the TRDCRi register are set to 001b (set the TRDi register to 000h by compare match in the TRDGRAi register).
Bits TOAi and TOBi in the TRDOCR register is set to 0 (initial output “L” to compare match), the TOCi bit is set to 1 (initial output “H” to compare match).
Bits IOA2 to IOA0 in the TRDIORAi register are set to 011b (TRDIOAi output inverted at TRDGRAi register compare match).
Bits IOB2 to IOB0 in the TRDIORAi register are set to 010b (TRDIOBi “H” output at TRDGRBi register compare match).
Bits IOC3 to IOC0 in the TRDIORCi register are set to 1001b (TRDIOCi “L” output at TRDGRCi register compare match).
Set bits IOD3 to IOD0 in the TRDIORCi register to 1000b (TRDGRDi register does not control TRDIOBi pin output, pin output at compare match is disabled).
i = 0 or 1
TRDSTR register
TRDSRi register
TRDSRi register
TRDSRi register
TRDIOBi output
TRDIOCi output
TRDIOAi output
Count source
TSTARTi bit in
IMFA bit in
IMFB bit in
IMFC bit in
Value in TRDi register
Operating Example of Output Compare Function
m
m
n
n
p
p
Initial output “H”
Initial output “L”
P+1
Initial output “L”
n+1
m+1
“L” output by compare match
M: Value set in TRDGRAi register
n: Value set in TRDGRBi register
p: Value set in TRDGRCi register
Set to 0 by a program
“H” output by compare match
Set to 0 by a program
Output inverted by compare match
Set to 0 by a program
m+1
Count
stops
Output level
Output level
Output level
held
held
held
restarts
Count
20. Timer RD