R5F21346CNFP#U0 Renesas Electronics America, R5F21346CNFP#U0 Datasheet - Page 384

• Manufacturer Part Number: R5F21346CNFP#U0
• Description: MCU 1KB FLASH 32K ROM 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/34Cr

Specifications of R5F21346CNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 43
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/34C Group
REJ09B0586-0100 Rev.1.00 Jan 13, 2010
Page 351 of 723
20.5.4
Notes:
20.5.5
After Reset
1. When the CSEL0 bit is set to 1, write 0 to the TSTART0 bit.
2. When the CSEL1 bit is set to 1, write 0 to the TSTART1 bit.
3. When the CSEL0 bit is set to 0 and the compare match signal (TRDIOA0) is generated, this bit is set to 0 (count
4. When the CSEL1 bit is set to 0 and the compare match signal (TRDIOA1) is generated, this bit is set to 0 (count
After Reset
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 0137h
Address 0138h
stops).
stops).
Set the TRDSTR register using the MOV instruction (do not use the bit handling instruction). Refer to 20.10.1
TRDSTR Register of Notes on Timer RD.
Symbol
Symbol
TSTART0 TRD0 count start flag
TSTART1 TRD1 count start flag
Symbol
Bit
Symbol
Bit
SYNC
BFC0
BFD0
BFC1
BFD1
CSEL0
CSEL1
Timer RD Start Register (TRDSTR) in PWM Mode
Timer RD Mode Register (TRDMR) in PWM Mode
—
—
—
—
—
—
—
BFD1
b7
b7
—
1
0
Timer RD synchronous bit
Nothing is assigned. If necessary, set to 0. When read, the content is 1.
TRDGRC0 register function select
bit
TRDGRD0 register function select
bit
TRDGRC1 register function select
bit
TRDGRD1 register function select
bit
TRD0 count operation select bit
TRD1 count operation select bit
Nothing is assigned. If necessary, set to 0. When read, the content is 1.
BFC1
b6
b6
—
1
0
Bit Name
Bit Name
BFD0
b5
—
b5
1
0
(3)
(4)
BFC0
b4
b4
—
1
0
0: Registers TRD0 and TRD1 operate independently
1: Registers TRD0 and TRD1 operate synchronously
0: General register
1: Buffer register of TRDGRA0 register
0: General register
1: Buffer register of TRDGRB0 register
0: General register
1: Buffer register of TRDGRA1 register
0: General register
1: Buffer register of TRDGRB1 register
CSEL1
0: Count stops
1: Count starts
0: Count stops
1: Count starts
0: Count stops at the compare match with the
1: Count continues after the compare match with
0: Count stops at the compare match with the
1: Count continues after the compare match with
b3
b3
—
1
1
TRDGRA0 register
the TRDGRA0 register
TRDGRA1 register
the TRDGRA1 register
CSEL0 TSTART1 TSTART0
b2
b2
—
1
1
(1)
(2)
Function
Function
b1
b1
—
0
1
SYNC
b0
b0
0
0
20. Timer RD
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
—