R5F21346CNFP#U0 Renesas Electronics America, R5F21346CNFP#U0 Datasheet - Page 393

MCU 1KB FLASH 32K ROM 48-LQFP

R5F21346CNFP#U0

Manufacturer Part Number
R5F21346CNFP#U0
Description
MCU 1KB FLASH 32K ROM 48-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/3x/34Cr
Datasheet

Specifications of R5F21346CNFP#U0

Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, PWM, Voltage Detect, WDT
Number Of I /o
43
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F21346CNFP#U0
Manufacturer:
Renesas Electronics America
Quantity:
135
Company:
Part Number:
R5F21346CNFP#U0
Manufacturer:
Renesas Electronics America
Quantity:
10 000
R8C/34C Group
REJ09B0586-0100 Rev.1.00 Jan 13, 2010
Page 360 of 723
Figure 20.16
TRDGRBi register
TRDGRBi register
TRDSTR register
TRDSTR register
TRDSRi register
TRDSRi register
TRDSRi register
TRDSRi register
TRDIOBi output
TRDIOBi output
TSTARTi bit in
TSTARTi bit in
Operating Example of PWM Mode (Duty 0%, Duty 100%)
IMFA bit in
IMFB bit in
IMFA bit in
IMFB bit in
Value in TRDi register
Value in TRDi register
0000h
0000h
i = 0 or 1
The above applies under the following conditions:
The EBi bit in the TRDOER1 register is set to 0 (enable TRDIOBi output).
The POLB bit in the TRDPOCRi register is set to 0 (active level “L”).
1
1
m
m
p
q
n
p
n
n
n
Rewrite by a program
Set to 0 by a program
m
Set to 0 by a program
Rewrite by a program
When compare matches with registers TRDGRAi and TRDGRBi are generated
simultaneously, the compare match with the TRDGRBi register has priority.
“L” is applied to the TRDIOBi output without any change.
Duty 100%
p (p>m)
Duty 0%
“L” is applied to TRDIOBi output by compare match
with the TRDGRBi register with no change.
p
m: Value set in TRDGRAi register
Since no compare match in the TRDGRBi register is
generated, “L” is not applied to the TRDIOBi output
Set to 0 by a program
Set to 0 by a program
q
20. Timer RD

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