R5F21346CNFP#U0 Renesas Electronics America, R5F21346CNFP#U0 Datasheet - Page 414

MCU 1KB FLASH 32K ROM 48-LQFP

R5F21346CNFP#U0

Manufacturer Part Number
R5F21346CNFP#U0
Description
MCU 1KB FLASH 32K ROM 48-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/3x/34Cr
Datasheet

Specifications of R5F21346CNFP#U0

Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, PWM, Voltage Detect, WDT
Number Of I /o
43
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F21346CNFP#U0
Manufacturer:
Renesas Electronics America
Quantity:
135
Company:
Part Number:
R5F21346CNFP#U0
Manufacturer:
Renesas Electronics America
Quantity:
10 000
R8C/34C Group
REJ09B0586-0100 Rev.1.00 Jan 13, 2010
Page 381 of 723
20.7.6
Notes:
After Reset
1. When setting bits CMD1 to CMD0 to 10b or 11b, the MCU enters complementary PWM mode in spite of the
2. Set bits CMD1 to CMD0 when both the TSTART0 and TSTART1 bits in the TRDSTR register are set to 0 (count
3. Set bits ADCAP1 to ADCAP0 in the ADMOD register to 01b (A/D conversion starts by conversion trigger from
4. When bits CMD1 to CMD0 are set to 00b (timer mode, PWM mode, or PWM3 mode), the setting of the PWM3 bit
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 013Ah
setting of the TRDPMR register.
stops).
timer RD).
is enabled.
Symbol
ADTRG
Symbol
STCLK
Bit
PWM3
CMD0
CMD1
ADEG
OLS0
OLS1
Timer RD Function Control Register (TRDFCR) in Complementary PWM
Mode
PWM3
b7
1
Combination mode select bit
Normal-phase output level select bit
(in reset synchronous PWM mode or
complementary PWM mode)
Counter-phase output level select bit
(in reset synchronous PWM mode or
complementary PWM mode)
A/D trigger enable bit
(in complementary PWM mode)
A/D trigger edge select bit
(in complementary PWM mode)
External clock input select bit
PWM3 mode select bit
STCLK
b6
0
Bit Name
ADEG
b5
0
(4)
ADTRG
(1, 2)
b4
0
OLS1
b1 b0
Other than above: Do not set.
0: Initial output “H”, Active level “L”
1: Initial output “L”, Active level “H”
0: Initial output “H”, Active level “L”
1: Initial output “L”, Active level “H”
0: Disable A/D trigger
1: Enable A/D trigger
0: A/D trigger is generated at compare match
1: A/D trigger is generated at underflow in the
0: External clock input disabled
1: External clock input enabled
This bit is disabled in complementary PWM mode.
1 0: Complementary PWM mode
1 1: Complementary PWM mode
b3
0
between registers TRD0 and TRDGRA0
TRD1 register
(transfer from the buffer register to the
general register at the underflow in the TRD1
register)
general register at the compare match with
registers TRD0 and TRDGRA0.)
(transfer from the buffer register to the
OLS0
b2
0
CMD1
Function
(3)
b1
0
CMD0
b0
0
20. Timer RD
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

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