R5F21346CNFP#U0 Renesas Electronics America, R5F21346CNFP#U0 Datasheet - Page 440

MCU 1KB FLASH 32K ROM 48-LQFP

R5F21346CNFP#U0

Manufacturer Part Number
R5F21346CNFP#U0
Description
MCU 1KB FLASH 32K ROM 48-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/3x/34Cr
Datasheet

Specifications of R5F21346CNFP#U0

Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, PWM, Voltage Detect, WDT
Number Of I /o
43
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

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Quantity
Price
Company:
Part Number:
R5F21346CNFP#U0
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Renesas Electronics America
Quantity:
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Company:
Part Number:
R5F21346CNFP#U0
Manufacturer:
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R8C/34C Group
REJ09B0586-0100 Rev.1.00 Jan 13, 2010
Page 407 of 723
Figure 20.23
20.8.17 Operating Example
TRDGRA0 register
TRDGRC0 register
TRDSTR register
TRDSTR register
TRDSR0 register
TRDSR0 register
TRDIOA0 output
TRDIOB0 output
TSTART0 bit in
Count source
j = either A or B
The above applies under the following conditions:
• Both the TOA0 and TOB0 bits in the TRDOCR register are set to 0 (initial output level “L”, output “H” by compare match with the
• The BFC0 bit in the TRDMR register is set to 1 (the TRDGRC0 register is used as the buffer register of the TRDGRA0 register).
CSEL0 bit in
TRDGRj1 register, output “L” at compare match with the TRDGRj0 register).
Operating Example of PWM3 Mode
IMFA bit in
IMFB bit in
Value in TRD0 register
FFFFh
0000h
m
n
p
q
Initial output “L”
Output “H” at compare
TRDGRA1 register
match with the
Set to 0 by a program
m
Output “L” at compare match
with the TRDGRA0 register
m
Transfer from buffer register to
general register
Set to 0 by a program
Transfer
q+1
p+1
Set to 0 by a program
n+1
p-q
m+1
Set to 0 by a program
m: Value set in TRDGRA0 register
n: Value set in TRDGRA1 register
p: Value set in TRDGRB0 register
q: Value set in TRDGRB1 register
m
Following data
Transfer from buffer register to
m-n
general register
Set to 0 by a program
Count stop
Transfer
20. Timer RD

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