R5F21346CNFP#U0 Renesas Electronics America, R5F21346CNFP#U0 Datasheet - Page 442

MCU 1KB FLASH 32K ROM 48-LQFP

R5F21346CNFP#U0

Manufacturer Part Number
R5F21346CNFP#U0
Description
MCU 1KB FLASH 32K ROM 48-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/3x/34Cr
Datasheet

Specifications of R5F21346CNFP#U0

Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, PWM, Voltage Detect, WDT
Number Of I /o
43
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

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Part Number:
R5F21346CNFP#U0
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R8C/34C Group
REJ09B0586-0100 Rev.1.00 Jan 13, 2010
Page 409 of 723
20.9
Figure 20.24
Table 20.17
Timer RD0
Timer RD1
Timer RD generates the timer RDi (i = 0 or 1) interrupt request from six sources for each timer RD0 and timer
RD1. The timer RD interrupt has 1 TRDiIC register (bits IR, and ILVL0 to ILVL2), and 1 vector for each timer
RD0 and timer RD1.
Table 20.17 lists the Registers Associated with Timer RD Interrupt, and Figure 20.24 shows a Block Diagram of
Timer RD Interrupt.
As with other maskable interrupts, the timer RD interrupt is controlled by the combination of the I flag, IR bit, bits
ILVL0 to ILVL2, and IPL. However, since the interrupt source (timer RD interrupt) is generated by a combination
of multiple interrupt request sources, the following differences from other maskable interrupts apply:
• When bits in the TRDSRi register corresponding to bits set to 1 in the TRDIERi register are set to 1 (enable
• When either bits in the TRDSRi register or bits in the TRDIERi register corresponding to bits in the TRDSRi
• When the conditions of other request sources are met, the IR bit remains 1.
• When multiple bits in the TRDIERi register are set to 1, which request source causes an interrupt is determined
• Since each bit in the TRDSRi register is not automatically set to 0 even if the interrupt is acknowledged, set each
Refer to Registers TRDSR0 to TRDSR1 in each mode (20.3.11, 20.4.14, 20.5.12, 20.6.10, 20.7.10, and 20.8.11)
for the TRDSRi register. Refer to Registers TRDIER0 to TRDIER1 in each mode (20.3.12, 20.4.15, 20.5.13,
20.6.11, 20.7.11, and 20.8.12) for the TRDIERi register.
Refer to 11.3 Interrupt Control for information on the TRDiIC register and 11.1.5.2 Relocatable Vector Tables
for the interrupt vectors.
interrupt), the IR bit in the TRDiIC register is set to 1 (interrupt requested).
register, or both of them, are set to 0, the IR bit is set to 0 (interrupt not requested). Therefore, even though the
interrupt is not acknowledged after the IR bit is set to 1, the interrupt request will not be maintained.
by the TRDSRi register.
bit to 0 in the interrupt routine. For information on how to set these bits to 0, refer to the descriptions of the
registers used in the different modes (20.3.11, 20.4.14, 20.5.12, 20.6.10, 20.7.10, and 20.8.11).
Timer RD Interrupt
Registers Associated with Timer RD Interrupt
Block Diagram of Timer RD Interrupt
i = 0 or 1
IMFA, IMFB, IMFC, IMFD, OVF, UDF: Bits in TRDSRi register
IMIEA, IMIEB, IMIEC, IMIED, OVIE: Bits in TRDIERi register
TRDSR0
TRDSR1
OVIE bit
UDF bit
OVF bit
Timer RDi
Status Register
IMIEC bit
IMIED bit
IMIEA bit
IMIEB bit
IMFC bit
IMFD bit
Timer RD
IMFA bit
IMFB bit
TRDIER0
TRDIER1
Interrupt Enable Register
Timer RD
Timer RDi interrupt request
(IR bit in TRDiIC register)
TRD0IC
TRD1IC
Interrupt Control Register
Timer RD
20. Timer RD

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