R5F21346CNFP#U0 Renesas Electronics America, R5F21346CNFP#U0 Datasheet - Page 447

• Manufacturer Part Number: R5F21346CNFP#U0
• Description: MCU 1KB FLASH 32K ROM 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/34Cr

Specifications of R5F21346CNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 43
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/34C Group
REJ09B0586-0100 Rev.1.00 Jan 13, 2010
Page 414 of 723
Figure 20.27
•
Select with bits CMD1 to CMD0 the timing of data transfer from the buffer register to the general register.
However, transfer takes place with the following timing in spite of the value of bits CMD1 to CMD0 in the
following cases:
Value in buffer register ≥ value in TRDGRA0 register:
Transfer take place at underflow of the TRD1 register.
After this, when the buffer register is set to 0001h or above and a smaller value than the value of the
TRDGRA0 register, and the TRD1 register underflows for the first time after setting, the value is transferred
to the general register. After that, the value is transferred with the timing selected by bits CMD1 to CMD0.
TRDGRD0 register
TRDGRB0 register
TRDIOD0 output
TRDIOB0 output
Complementary PWM Mode
Operation when Value in Buffer Register ≥ Value in TRDGRA0 Register in
The above applies under the following conditions:
• Bits CMD1 to CMD0 in the TRDFCR register are set to 11b (data in the buffer register is transferred at compare match
• Both the OSL0 and OLS1 bits in the TRDFCR register are set to 1 (active ‘H” for normal-phase and counter-phase).
between registers TRD0 and TRDGRA0 in complementary PWM mode).
Transfer with timing set by
bits CMD1 to CMD0
0000h
m+1
n3
n2
n1
Transfer
n2
n1
n2
Transfer at
underflow of TRD1
register because of
n3 > m
n3
Transfer
n3
Transfer at
underflow of TRD1
register because
of first setting to
n2 < m
Transfer
n2
m: Value set in TRDGRA0 register
n2
n1
Transfer with timing set by
bits CMD1 to CMD0
Transfer
n1
Count value in TRD0
register
Count value in TRD1
register
20. Timer RD