R5F21346CNFP#U0 Renesas Electronics America, R5F21346CNFP#U0 Datasheet - Page 505

MCU 1KB FLASH 32K ROM 48-LQFP

R5F21346CNFP#U0

Manufacturer Part Number
R5F21346CNFP#U0
Description
MCU 1KB FLASH 32K ROM 48-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/3x/34Cr
Datasheet

Specifications of R5F21346CNFP#U0

Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, PWM, Voltage Detect, WDT
Number Of I /o
43
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

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Price
Company:
Part Number:
R5F21346CNFP#U0
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Part Number:
R5F21346CNFP#U0
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R8C/34C Group
REJ09B0586-0100 Rev.1.00 Jan 13, 2010
Page 472 of 723
Figure 23.5
23.3.3
23.3.4
Use the UFORM bit in the U2C0 register to select the transfer format. Figure 23.5 shows the Transfer Format.
In continuous receive mode, receive operation is enabled when the receive buffer register is read. It is not
necessary to write dummy data to the transmit buffer register to enable receive operation in this mode.
However, a dummy read of the receive buffer register is required when starting the operating mode.
When the U2RRM bit in the U2C1 register is set to 1 (continuous receive mode), the TI bit in the U2C1 register
is set to 0 (data present in the U2TB register) by reading the U2RB register. If the U2RRM bit is set to 1, do not
write dummy data to the U2TB register by a program.
LSB First/MSB First Select Function
Continuous Receive Mode
(1) UFORM Bit in U2C0 Register = 0 (LSB first)
(2) UFORM Bit in U2C0 Register = 1 (MSB first)
The above applies when:
Transfer Format
CLK2
TXD2
RXD2
CLK2
TXD2
RXD2
CKPOL bit in U2C0 register = 0
(transmit data output at the falling edge and receive data input
U2LCH bit in U2C1 register = 0 (not inverted)
at the rising edge of the transfer clock)
D7
D0
D0
D7
D6
D1
D1
D6
D5
D2
D2
D5
D4
D3
D3
D4
D3
D4
D3
D4
D2
D5
D5
D2
D6
D6
D1
D1
D7
D7
D0
D0
23. Serial Interface (UART2)

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