R5F21346CNFP#U0 Renesas Electronics America, R5F21346CNFP#U0 Datasheet - Page 523

MCU 1KB FLASH 32K ROM 48-LQFP

R5F21346CNFP#U0

Manufacturer Part Number
R5F21346CNFP#U0
Description
MCU 1KB FLASH 32K ROM 48-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/3x/34Cr
Datasheet

Specifications of R5F21346CNFP#U0

Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, PWM, Voltage Detect, WDT
Number Of I /o
43
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

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Company:
Part Number:
R5F21346CNFP#U0
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Part Number:
R5F21346CNFP#U0
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R8C/34C Group
REJ09B0586-0100 Rev.1.00 Jan 13, 2010
Page 490 of 723
23.5.3
23.5.4
23.5.5
23.5.6
The transfer clock is used to transmit and receive data as is shown in Figure 23.14 Transfer to U2RB Register
and Interrupt Timing.
The CSC bit in the U2SMR2 register is used to synchronize an internally generated clock (internal SCL2) and
an external clock supplied to the SCL2 pin. When the CSC bit is set to 1 (clock synchronization enabled), if a
falling edge on the SCL2 pin is detected while the internal SCL2 is high, the internal SCL2 goes low. The value
in the U2BRG register is reloaded and counting of the low-level intervals starts. If the internal SCL2 changes
state from low to high while the SCL2 pin is low, counting stops. If the SCL2 pin goes high, counting restarts.
In this way, the UART2 transfer clock is equivalent to AND of the internal SCL2 and the clock signal applied to
the SCL2 pin. The transfer clock works from a half cycle before the falling edge of the internal SCL2 1st bit to
the rising edge of the 9th bit. To use this function, select an internal clock for the transfer clock.
The SWC bit in the U2SMR2 register determines whether the SCL2 pin is fixed low or freed from low-level
output at the falling edge of the 9th clock pulse.
If the SCLHI bit in the U2SMR4 register is set to 1 (enabled), SCL2 output is turned off (placed in the high-
impedance state) when a stop condition is detected.
Setting the SWC2 bit in the U2SMR2 register to 1 (“L” output) makes it possible to forcibly output a low-level
signal from the SCL2 pin even while sending or receiving data. Setting the SWC2 bit to 0 (transfer clock)
allows the transfer clock to be output from or supplied to the SCL2 pin, instead of outputting a low-level signal.
If the SWC9 bit in the U2SMR4 register is set to 1 (SCL “L” hold enabled) when the CKPH bit in the U2SMR3
register is 1, the SCL2 pin is fixed low at the falling edge of the clock pulse next to the 9th. Setting the SWC9
bit to 0 (SCL “L” hold disabled) frees the SCL2 pin from low-level output.
The data written to bits b7 to b0 (D7 to D0) in the U2TB register is output in descending order from D7.
The 9th bit (D8) is ACK or NACK.
Set the initial value of SDA2 transmit output when IICM is set to 1 (I
U2MR register are set to 000b (serial interface disabled).
Bits DL2 to DL0 in the U2SMR3 register allow addition of no delays or a delay of 2 to 8 U2BRG count source
clock cycles to the SDA2 output.
Setting the SDHI bit in the U2SMR2 register to 1 (SDA output disabled) forcibly places the SDA2 pin in the
high-impedance state. Do not write to the SDHI bit at the rising edge of the UART2 transfer clock.
When the IICM2 bit is set to 0, the 1st to 8th bits (D7 to D0) of received data are stored in bits b7 to b0 in the
U2RB register. The 9th bit (D8) is ACK or NACK.
When the IICM2 bit is set to 1, the 1st to 7th bits (D7 to D1) of received data are stored in bits b6 to b0 in the
U2RB register and the 8th bit (D0) is stored in bit b8 in the U2RB register. Even when the IICM2 bit is set to 1,
if the CKPH bit is 1, the same data as when the IICM2 bit is 0 can be read by reading the U2RB register after
the rising edge of 9th bit of the clock.
If the STSPSEL bit in the U2SMR4 register is set to 0 (start and stop conditions not output) and the ACKC bit
in the U2SMR4 register is set to 1 (ACK data output), the value of the ACKD bit in the U2SMR4 register is
output from the SDA2 pin.
If the IICM2 bit is set to 0, a NACK interrupt request is generated if the SDA2 pin remains high at the rising
edge of the 9th bit of transmit clock pulse. An ACK interrupt request is generated if the SDA2 pin is low at the
rising edge of the 9th bit of the transmit clock.
If ACK2 (UART2 reception) is selected to generate a DTC request source, a DTC transfer can be activated by
detection of an acknowledge.
Transfer Clock
SDA Output
SDA Input
ACK and NACK
2
C mode) and bits SMD2 to SMD0 in the
23. Serial Interface (UART2)

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