R5F21346CNFP#U0 Renesas Electronics America, R5F21346CNFP#U0 Datasheet - Page 553

• Manufacturer Part Number: R5F21346CNFP#U0
• Description: MCU 1KB FLASH 32K ROM 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/34Cr

Specifications of R5F21346CNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 43
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/34C Group
REJ09B0586-0100 Rev.1.00 Jan 13, 2010
Page 520 of 723
Figure 25.7
25.4.3
RDRF bit in
SSSR register
RSSTP bit in
SSCRH register
Figure 25.7 shows an Example of Synchronous Serial Communication Unit Operation for Data Reception
(Clock Synchronous Communication Mode, 8-Bit SSU Data Transfer Length). During data reception,
synchronous serial communication unit operates as described below (The data transfer length can be set from 8
to 16 bits using the SSBR register).
When the synchronous serial communication unit is set as the master device, it outputs a synchronous clock and
inputs data. When synchronous serial communication unit is set as a slave device, it inputs data synchronized
with the input clock.
When synchronous serial communication unit is set as a master device, it outputs a receive clock and starts
receiving by performing dummy read of the SSRDR register.
After 8 bits of data are received, the RDRF bit in the SSSR register is set to 1 (data in the SSRDR register) and
receive data is stored in the SSRDR register. When the RIE bit in the SSER register is set to 1 (RXI and OEI
interrupt requests enabled), the RXI interrupt request is generated. If the SSDR register is read, the RDRF bit is
automatically set to 0 (no data in the SSRDR register).
Read the receive data after setting the RSSTP bit in the SSCRH register to 1 (after receiving 1 byte of data, the
receive operation is completed). Synchronous serial communication unit outputs a clock for receiving 8 bits of
data and stops. After that, set the RE bit in the SSER register to 0 (receive disabled) and the RSSTP bit to 0
(receive operation is continued after receiving the 1 byte of data) and read the receive data. If the SSRDR
register is read while the RE bit is set to 1 (receive enabled), a receive clock is output again.
When the 8th clock rises while the RDRF bit is set to 1, the ORER bit in the SSSR register is set to 1 (overrun
error: OEI) and the operation is stopped. When the ORER bit is set to 1, receive cannot be performed. Confirm
that the ORER bit is set to 0 before restarting receive.
Figure 25.8 shows a Sample Flowchart of Data Reception (MSS = 1) (Clock Synchronous Communication
Mode).
Processing
by program
• SSUMS = 0 (clock synchronous communication mode), CPHS = 0 (data download at
even edges), CPOS bit = 0 (“H” when clock stops), and BS3 to BS0 = 1000b (8 bits)
Data Reception
SSCK
SSI
Example of Synchronous Serial Communication Unit Operation for Data Reception
(Clock Synchronous Communication Mode, 8-Bit SSU Data Transfer Length)
Dummy read in
SSRDR register
b0
RXI interrupt request
generation
1 frame
Read data in SSRDR
register
b7
b0
RXI interrupt request
generation
25. Synchronous Serial Communication Unit (SSU)
1 frame
Set RSSTP bit to 1
BS0 to BS3: Bits in SSBR register
CPHS, CPOS: Bits in SSMR register
SSUMS: Bit in SSMR2 register
b7
b0
Read data in
SSRDR register
RXI interrupt request
generation
b7