R5F21346CNFP#U0 Renesas Electronics America, R5F21346CNFP#U0 Datasheet - Page 563

• Manufacturer Part Number: R5F21346CNFP#U0
• Description: MCU 1KB FLASH 32K ROM 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/34Cr

Specifications of R5F21346CNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 43
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/34C Group
REJ09B0586-0100 Rev.1.00 Jan 13, 2010
Page 530 of 723
Figure 25.13
25.5.4
When setting the SSUMS bit in the SSMR2 register to 1 (4-wire bus communication mode) and the CSS1 bit in
the SSMR2 register to 1 (functions as SCS output pin), set the MSS bit in the SSCRH register to 1 (operates as
the master device) and check the arbitration of the SCS pin before starting serial transfer. If synchronous serial
communication unit detects that the synchronized internal SCS signal is held “L” in this period, the CE bit in
the SSSR register is set to 1 (conflict error) and the MSS bit is automatically set to 0 (operates as a slave
device).
Figure 25.13 shows the Arbitration Check Timing.
Future transmit operations are not performed while the CE bit is set to 1. Set the CE bit to 0 (no conflict error)
before starting transmission.
(synchronization)
SSCRH register
Transfer start
Internal SCS
SCS Pin Control and Arbitration
SCS output
MSS bit in
SCS input
Arbitration Check Timing
CE
High-impedance
During arbitration detection
Data write to
SSTDR register
25. Synchronous Serial Communication Unit (SSU)
Maximum time of SCS internal
synchronization