R5F21346CNFP#U0 Renesas Electronics America, R5F21346CNFP#U0 Datasheet - Page 580

MCU 1KB FLASH 32K ROM 48-LQFP

R5F21346CNFP#U0

Manufacturer Part Number
R5F21346CNFP#U0
Description
MCU 1KB FLASH 32K ROM 48-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/3x/34Cr
Datasheet

Specifications of R5F21346CNFP#U0

Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, PWM, Voltage Detect, WDT
Number Of I /o
43
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F21346CNFP#U0
Manufacturer:
Renesas Electronics America
Quantity:
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Company:
Part Number:
R5F21346CNFP#U0
Manufacturer:
Renesas Electronics America
Quantity:
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R8C/34C Group
REJ09B0586-0100 Rev.1.00 Jan 13, 2010
Page 547 of 723
26.3.3
Table 26.6
STIE, NAKIE, RIE, TEIE, TIE: Bits in ICIER register
AL, STOP, NACKF, RDRF, TEND, TDRE: Bits in ICSR register
Transmit data empty
Transmit ends
Receive data full
Stop condition detection
NACK detection
Arbitration lost/overrun error
The I
when the clock synchronous serial format is used.
Table 26.6 lists the Interrupt Requests of I
Because these interrupt requests are allocated at the I
determined bit by bit.
When generation conditions listed in Table 26.6 are met, an I
the interrupt generation conditions to 0 by the I
Note that bits TDRE and TEND are automatically set to 0 by writing transmit data to the ICDRT register and
that the RDRF bit is automatically set to 0 by reading the ICDRR register. Especially, the TDRE bit is set to 0
when writing transmit data to the ICDRT register and set to 1 when transferring data from the ICDRT register to
the ICDRS register. If the TDRE bit is further set to 0, additional 1 byte may be transmitted.
Also, set the STIE bit to 1 (stop condition detection interrupt request enabled) when the STOP bit is set to 0.
2
Interrupt Requests
C bus interface has six interrupt requests when the I
Interrupt Request
Interrupt Requests of I
TXI
TEI
RXI
STPI
NAKI
2
C bus Interface
2
TIE = 1 and TDRE = 1
TEIE = 1 and TEND = 1
RIE = 1 and RDRF = 1
STIE = 1 and STOP = 1
NAKIE = 1 and AL = 1
(or NAKIE = 1 and NACKF = 1)
C bus Interface.
2
C bus interface interrupt routine.
Generation Condition
2
C bus interface interrupt vector table, the source must be
2
2
C bus format is used and four interrupt requests
C bus interface interrupt request is generated. Set
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
I
2
C bus
26. I
Format
2
Synchronous
Enabled
Enabled
Enabled
Disabled
Disabled
Enabled
C bus Interface
Clock
Serial

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