R5F21346CNFP#U0 Renesas Electronics America, R5F21346CNFP#U0 Datasheet - Page 606

• Manufacturer Part Number: R5F21346CNFP#U0
• Description: MCU 1KB FLASH 32K ROM 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/34Cr

Specifications of R5F21346CNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 43
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/34C Group
REJ09B0586-0100 Rev.1.00 Jan 13, 2010
Page 573 of 723
27.4
Figure 27.2
27.4.1
TRAIC register
LINST register
Figure 27.2 shows an Operating Example during Header Field Transmission in master mode. Figures 27.3 and
27.4 show Examples of Header Field Transmission Flowchart.
During header field transmission, the hardware LIN operates as follows:
(1) When 1 is written to the TSTART bit in the TRACR register for timer RA, a “L” level is output from the
(2) When timer RA underflows, the TXD0 pin output is inverted and the SBDCT flag in the LINST register is
(3) The hardware LIN transmits “55h” via UART0.
(4) After the hardware LIN completes transmitting “55h”, it transmits an ID field via UART0.
(5) After the hardware LIN completes transmitting the ID field, it performs communication for a response
SBDCT flag in
Function Description
TXD0 pin for the period set in registers TRAPRE and TRA for timer RA.
set to 1. If the SBIE bit in the LINCR register is set to 1, a timer RA interrupt is generated.
field.
TXD0 pin
IR bit in
Master Mode
Operating Example during Header Field Transmission
The above applies when:
LINE = 1, MST = 1, SBIE = 1
(1)
Synch Break
(2)
(3)
Set to 0 when an interrupt request is acknowledged
or by a program.
1 is written to B1CLR bit in LINST register.
Synch Field
(4)
IDENTIFIER
27. Hardware LIN
(5)