R5F21346CNFP#U0 Renesas Electronics America, R5F21346CNFP#U0 Datasheet - Page 607

• Manufacturer Part Number: R5F21346CNFP#U0
• Description: MCU 1KB FLASH 32K ROM 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/34Cr

Specifications of R5F21346CNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 43
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/34C Group
REJ09B0586-0100 Rev.1.00 Jan 13, 2010
Page 574 of 723
Figure 27.3
Notes:
Timer RA Set to timer mode
Timer RA Set the pulse output level from low to start
Timer RA TRAIO pin assigned to P1_5
UART0
INT1
Timer RA Set the count source (f1, f2, f8, fOCO)
Timer RA Set the Synch Break width
UART0
UART0
UART0
Hardware LIN Set the LIN operation to stop
Hardware LIN Set to master mode.
Hardware LIN Set bus collision detection to enable
Hardware LIN Set the LIN operation to start
Hardware LIN Set interrupts to enable
Hardware LIN Clear the status flags
1. When the previous communication completes normally and header field transmission is
2. Although the timer-associated registers (TRAMR and TRAIOC) are set before the
performed again with the same settings, the above settings can be omitted.
TRASR register is set, there is no problem with this flow for the hardware LIN.
Header Field Transmission Flowchart Example (1)
Set to transmit/receive mode
(Transfer data 8 bits long, internal clock, 1 stop bit, parity
disabled)
U0MR register
Set the BRG count source (f1, f8, f32)
Bits CLK0 and CLK1 in U0C0 register
Set the bit rate
U0BRG register
Bits TMOD2 to TMOD0 in TRAMR register ← 000b
TEDGSEL bit in TRAIOC register ← 1
Bits TRAIOSEL1 to TRAIOSEL0 in TRASR register ← 10b
RXD0 pin assigned to P1_5
RXD0SEL0 bit in U0SR register ← 1
INT1 pin assigned to P1_5
Bits INT1SEL1 and INT1SEL0 in INTSR register ← 01b
Bits TCK0 to TCK2 in TRAMR register
TRAPRE register
TRA register
(Bus collision detection, Synch Break detection,
Synch Field measurement)
Bits BCIE, SBIE, SFIE in LINCR register
LINCR register LINE bit ← 0
MST bit in LINCR register ← 1
BCE bit in LINCR2 register ← 1
LINE bit in LINCR register ← 1
(Bus collision detection, Synch Break detection,
Synch Field measurement)
Bits B2CLR, B1CLR, B0CLR in LINST register ← 1
A
(1, 2)
(1, 2)
(1, 2)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Set the TIOSEL bit in the
TRAIOC register to 1 to select
the hardware LIN function.
If the wake-up function is not
necessary, the setting of the
INT1 pin can be omitted.
Set the count source and
registers TRA and TRAPRE
as appropriate for the Synch
Break period.
Set the BRG count source
and the U0BRG register as
appropriate for the bit rate.
In master mode, the Synch
Field measurement-completed
interrupt cannot be used.
27. Hardware LIN