R5F21346CNFP#U0 Renesas Electronics America, R5F21346CNFP#U0 Datasheet - Page 610

• Manufacturer Part Number: R5F21346CNFP#U0
• Description: MCU 1KB FLASH 32K ROM 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/34Cr

Specifications of R5F21346CNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 43
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/34C Group
REJ09B0586-0100 Rev.1.00 Jan 13, 2010
Page 577 of 723
Figure 27.6
Notes:
Timer RA
Hardware LIN
Hardware LIN
Hardware LIN
Hardware LIN
Hardware LIN
Timer RA
Timer RA
UART0
INT1
Timer RA
Timer RA
1. When the previous communication completes normally and header field reception is
2. Although the timer-associated registers (TRAMR and TRAIOC) are set before the
performed again with the same settings, the above settings can be omitted.
TRASR register is set, there is no problem with this flow for the hardware LIN.
TRAIO pin assigned to P1_5
Bits TRAIOSEL1 to TRAIOSEL0 in TRASR register ← 10b
RXD0 pin assigned to P1_5
RXD0SEL0 bit in U0SR register ← 1
INT1 pin assigned to P1_5
Bits INT1SEL1 and INT1SEL0 in INTSR register ← 01b
Set the pulse width measurement level to low
TEDGSEL bit in TRAIOC register ← 0
Set the count source (f1, f2, f8, fOCO)
Bits TCK0 to TCK2 in TRAMR register
Set the Synch Break width
TRAPRE register
TRA register
Set to pulse width measurement mode
Bits TMOD2 to TMOD0 in TRAMR register ← 011b
Header Field Reception Flowchart Example (1)
(After Synch Break detection, or after Synch Field
measurement)
SBE bit in LINCR register
Set the RXD0 input unmasking timing
Set interrupts to enable
Bits BCIE, SBIE, SFIE in LINCR register
Set the LIN operation to stop
LINE bit in LINCR register ← 0
Set to slave mode
MST bit in LINCR register ← 0
Set the LIN operation to start
LINE bit in LINCR register ← 1
(Bus collision detection, Synch Break detection, Synch
Field measurement)
A
(1, 2)
(1, 2)
(1, 2)
(1)
(1)
(1)
(1)
(1)
(1)
Set the TIOSEL bit in the
TRAIOC register to 1 to select the
hardware LIN function.
If the wake-up function is not
necessary, the setting of the INT1
pin can be omitted.
Set the count source and registers
TRA and TRAPRE as appropriate
for the Synch Break period.
Select the timing at which to
unmask the RXD0 input for UART0.
If the RXD0 input is chosen to be
unmasked after Synch Break
detection, the Synch Field signal is
also input to UART0.
27. Hardware LIN