R5F21346CNFP#U0 Renesas Electronics America, R5F21346CNFP#U0 Datasheet - Page 627

• Manufacturer Part Number: R5F21346CNFP#U0
• Description: MCU 1KB FLASH 32K ROM 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/34Cr

Specifications of R5F21346CNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 43
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/34C Group
REJ09B0586-0100 Rev.1.00 Jan 13, 2010
Page 594 of 723
Figure 28.4
28.3.3
28.3.3.1
28.3.3.2
A software trigger, trigger from timer RD or timer RC, and external trigger are used as A/D conversion start
triggers.
Figure 28.4 shows the Block Diagram of A/D Conversion Start Control Unit.
A software trigger is selected when bits ADCAP1 to ADCAP0 in the ADMOD register are set to 00b (software
trigger).
The A/D conversion starts when the ADST bit in the ADCON0 register is set to 1 (A/D conversion starts).
This trigger is selected when bits ADCAP1 to ADCAP0 in the ADMOD register are set to 01b (timer RD).
To use this function, make sure the following conditions are met.
•
•
•
•
When the IMFj bit in the TRDSRk register is changed from 0 to 1, A/D conversion starts.
Refer to 20. Timer RD, 20.4 Output Compare Function, 20.5 PWM Mode, 20.6 Reset Synchronous PWM
Mode, 20.7 Complementary PWM Mode, 20.8 PWM3 Mode for the details of timer RD and the output
compare function (timer mode, PWM mode, reset synchronous PWM mode, complementary PWM mode, and
PWM3 mode).
Bits ADCAP1 to ADCAP0 in the ADMOD register are set to 01b (timer RD).
Timer RD is used in the output compare function (timer mode, PWM mode, reset synchronous PWM mode,
complementary PWM mode, and PWM3 mode).
The ADTRGjkE bit (j = A, B, C, D, k = 0 or 1) in the TRDADCR register is set to 1 (A/D trigger occurs at
compare match with TRDGRjk register).
The ADST bit in the ADCON0 register is set to 1 (A/D conversion starts).
(TRDSRk register)
(TRCSR register)
A/D Conversion Start Condition
ADTRG pin
j = A, B, C, D k = 0 to 1
ADCAP1 to ADCAP0: Bits in ADMOD register
ADST: Bit in ADCON0 register
ADTRGjkE: Bit in TRDADCR register
ADTRGjE: Bit in TRCADCR register
INT0EN: Bit in INTEN register
IMFj: Bit in TRDSRk register
IMFj: Bit in TRCSR register
PD4_5: Bit in PD4 register
Software Trigger
Trigger from Timer RD
Block Diagram of A/D Conversion Start Control Unit
PD4_5
IMFj
IMFj
ADTRGjkE
ADTRGjE
INT0EN
ADST
= 00b
= 01b
= 10b
= 11b
ADCAP1 to ADCAP0
A/D conversion start trigger
28. A/D Converter