R5F21346CNFP#U0 Renesas Electronics America, R5F21346CNFP#U0 Datasheet - Page 67

• Manufacturer Part Number: R5F21346CNFP#U0
• Description: MCU 1KB FLASH 32K ROM 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/34Cr

Specifications of R5F21346CNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 43
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/34C Group
REJ09B0586-0100 Rev.1.00 Jan 13, 2010
Page 34 of 723
5.3
Figure 5.6
When the RESET pin is connected to the VCC pin via a pull-up resistor, and the VCC pin voltage level rises, the
power-on reset function is enabled and the MCU resets its pins, CPU, and SFR. When a capacitor is connected to
the RESET pin, too, always keep the voltage to the RESET pin 0.8VCC or more.
When the input voltage to the VCC pin reaches the Vdet0 level or above, the low-speed on-chip oscillator clock
starts counting. When the low-speed on-chip oscillator clock count reaches 32, the internal reset signal is held “H”
and the MCU enters the reset sequence (refer to Figure 5.3). The low-speed on-chip oscillator clock with no
division is automatically selected as the CPU clock after reset.
Refer to 4. Special Function Registers (SFRs) for the states of the SFR after power-on reset.
To use the power-on reset function, enable voltage monitor 0 reset by setting the LVDAS bit in the OFS register to
0.
Figure 5.6 shows an Example of Power-On Reset Circuit and Operation.
Power-On Reset Function
Notes:
1. V
2. t
Example of Power-On Reset Circuit and Operation
3. To use the power-on reset function, enable voltage monitor 0 reset by setting the
6. Voltage Detection Circuit for details.
voltage (0.5 V) to enable a power-on reset. When turning on the power after it falls
with voltage monitor 0 reset disabled, maintain t
LVDAS bit in the OFS register to 0.
w(por)
det0
indicates the voltage detection level of the voltage detection 0 circuit. Refer to
reset signal
indicates the duration the external power V
Power V
External
4.7 kΩ
(reference)
Internal
V
det0
0.5V
CC
(1)
t
w(por)
VCC
RESET
(2)
w(por)
CC
must be held below the valid
f
OCO-S
for 1 ms or more.
1
× 32
5. Resets