R5F21275SNFP#U0 Renesas Electronics America, R5F21275SNFP#U0 Datasheet - Page 344

IC R8C/27 MCU FLASH 32LQFP

R5F21275SNFP#U0

Manufacturer Part Number
R5F21275SNFP#U0
Description
IC R8C/27 MCU FLASH 32LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/27r
Datasheet

Specifications of R5F21275SNFP#U0

Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
LED, POR, Voltage Detect, WDT
Number Of I /o
25
Program Memory Size
24KB (24K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
32-LQFP
For Use With
R0K521276S000BE - KIT DEV RSK-R8C/26-29R0E521000EPB00 - PROBE EMULATOR FOR PC7501
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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R8C/26 Group, R8C/27 Group
Rev.2.10
REJ09B0278-0210
17.3
Figure 17.2
LIN Control Register
The hardware LIN contains the registers listed below.
These registers are detailed in Figures 17.2 and 17.3.
b7 b6 b5 b4 b3 b2 b1 b0
NOTES:
• LIN Control Register (LINCR)
• LIN Status Register (LINST)
1.
2.
3.
Register Configuration
After setting the LSTART bit, confirm that the RXDSF flag is set to 1 before Synch Break input starts.
Before changing LIN operation modes, temporarily stop the LIN operation (LINE bit = 0).
Inputs to timer RA and UART0 are prohibited immediately after this bit is set to 1. (Refer to Figure 17.5 Exam ple of
Header Field Transm ission Flow chart (1) and Figure 17.9 Exam ple of Header Field Reception Flow chart
(2) .)
Sep 26, 2008
LINCR Register
Bit Symbol
LSTART
Symbol
RXDSF
LINCR
SFIE
SBIE
BCIE
MST
SBE
LINE
Page 325 of 453
Synch Field measurement-
completed interrupt enable bit
Synch Break detection interrupt
enable bit
Bus collision detection interrupt
enable bit
RXD0 input status flag
Synch Break detection start bit
RXD0 input unmasking timing
select bit (effective only in slave
mode)
LIN operation mode setting bit
LIN operation start bit
Address
Bit Name
0106h
(2)
(1)
0 : Disables Synch Field measurement-
1 : Enables Synch Field measurement-
0 : Disables Synch Break detection interrupt
1 : Enables Synch Break detection interrupt
0 : Disables bus collision detection interrupt
1 : Enables bus collision detection interrupt
0 : RXD0 input enabled
1 : RXD0 input disabled
When this bit is set to 1, timer RA input is
enabled and RXD0 input is disabled.
When read, the content is 0.
0 : Unmasked after Synch Break is detected
1 : Unmasked after Synch Field measurement
0 : Slave mode
1 : Master mode
0 : Causes LIN to stop
1 : Causes LIN to start operating
completed interrupt
completed interrupt
is completed
(Synch Break detection circuit actuated)
(Timer RA output OR’ed w ith TXD0)
After Reset
Function
00h
(3)
17. Hardware LIN
RW
RW
RW
RW
RW
RW
RW
RW
RO

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