R5F21274SDFP#U0 Renesas Electronics America, R5F21274SDFP#U0 Datasheet - Page 89

• Manufacturer Part Number: R5F21274SDFP#U0
• Description: IC R8C/27 MCU FLASH 32LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/27r

Specifications of R5F21274SDFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 25
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• For Use With: R0K521276S000BE - KIT DEV RSK-R8C/26-29R0E521000EPB00 - PROBE EMULATOR FOR PC7501
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/26 Group, R8C/27 Group
Rev.2.10
REJ09B0278-0210
Table 7.23
X: 0 or 1
NOTE:
Table 7.24
NOTE:
Table 7.25
X: 0 or 1
NOTES:
Table 7.26
X: 0 or 1
NOTES:
Register
Register
Setting
Setting
Register
Register
value
value
Setting
Setting
3. Set the TOPCR bit in the TRAIOC register to 0 in modes except for pulse output mode.
1. Pulled up by setting the PU06 bit in the PUR0 register to 1.
1. Set the TOCNT bit in the TRBIOC register to 0 in modes except for programmable waveform generation mode.
1. Pulled up by setting the PU06 bit in the PUR0 register to 1.
2. Set the SSISEL bit in the PMR register to 0 (P3_3).
3. When the SOOS bit is set to 1 (N-channel open drain output) and BIDE bit is set to 0 (standard mode) in the SSMR2 register,
1. Pulled up by setting the PU07 bit in the PUR0 register to 1.
2. N-channel open drain output by setting the CSOS bit in the SSMR2 register to 1 (N-channel open drain output).
value
value
Bit
Bit
Bit
Bit
this pin is set to N-channel open drain output.
Sep 26, 2008
TRBOSEL
PD3_3
PINSR2
PD3_4
PD3
PD3
X
X
0
1
0
0
Port P3_1/TRBO
TRBO Pin Setting
Port P3_3/INT3/SSI/TRCCLK
Port P3_4/SDA/SCS/(TRCIOC)
0
1
X
0
X
X
X
PD3_1
0
0
0
0
PD3
X
0
1
IICSEL
PMR
IICSEL
X
X
X
X
0
0
PMR
X
X
0
1
0
1
0
0
1
Page 70 of 453
TOCNT
TRBIOC
Communication Modes and I/O Pins.)
Clock Synchronous Serial I/O with Chip
SSI output control
Other than above
0
0
0
1
Refer to Table 7.24 TRBO Pin Setting
Other than TRBO usage conditions
Other than TRBO usage conditions
ICCR1
(1)
ICE
Select (Refer to Table 16.4
X
X
X
X
0
0
0
0
1
Association between
0
0
0
0
1
0
Timer RB Setting
TMOD1
CSS1
0
1
1
0
X
0
0
0
0
0
0
1
1
SSMR2
−
TRBMR
SSI input control
CSS0
X
0
0
0
0
0
0
0
1
TMOD0
0
0
0
0
0
1
1
0
1
1
Refer to Table 7.27 TRCIOC Pin Setting TRCIOC output
Refer to Table 7.27 TRCIOC Pin Setting TRCIOC input
Other than TRCIOC usage conditions
Other than TRCIOC usage conditions
Other than TRCIOC usage conditions
Other than TRCIOC usage conditions
Other than TRCIOC usage conditions
Other than TRCIOC usage conditions
Other than TRCIOC usage conditions
TCK2
Programmable waveform generation mode
Programmable one-shot generation mode
Programmable wait one-shot generation mode
P3_1 output port
Other than TRBO usage conditions
1
Input port
Output port
TRBO output
Other than 101b
Other than 101b
Other than 101b
Other than 101b
Other than 101b
Timer RC setting
TRCCR1
TCK1
0
(1)
−
TCK0
Function
1
Function
7. Programmable I/O Ports
INT3EN
INTEN
0
0
1
0
0
0
Input port
Output port
SCS output
SCS input
SDA input/output
Input port
Output port
INT3 input
TRCCLK input
SSI output
SSI input
Function
Function
(2)
(1)
(1)
(1)
(1)
(2)
(2)
(3)
(1)
(1)