R5F21274JFP#U0 Renesas Electronics America, R5F21274JFP#U0 Datasheet - Page 279

MCU FLASH 2K FLASH 16K 32LQFP

R5F21274JFP#U0

Manufacturer Part Number
R5F21274JFP#U0
Description
MCU FLASH 2K FLASH 16K 32LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/27r
Datasheet

Specifications of R5F21274JFP#U0

Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
LED, POR, Voltage Detect, WDT
Number Of I /o
25
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F21274JFP#U0
Manufacturer:
Renesas Electronics America
Quantity:
10 000
R8C/26 Group, R8C/27 Group
Rev.2.10
REJ09B0278-0210
16.2
Table 16.2
NOTE:
Transfer data format
Operating modes
Master/slave device
I/O pins
Transfer clocks
Receive error
detection
Multimaster error
detection
Interrupt requests
Select functions
Clock synchronous serial I/O with chip select supports clock synchronous serial data communication.
Table 16.2 lists the Specifications of Clock Synchronous Serial I/O with Chip Select and Figure 16.1 shows a
Block Diagram of Clock Synchronous Serial I/O with Chip Select. Figures 16.2 to 16.9 show the registers
associated with clock synchronous serial I/O with chip select.
1. Clock synchronous serial I/O with chip select has only one interrupt vector table.
Clock Synchronous Serial I/O with Chip Select (SSU)
Sep 26, 2008
Item
Specifications of Clock Synchronous Serial I/O with Chip Select
Page 260 of 453
• Clock synchronous communication mode
• 4-wire bus communication mode (including bidirectional communication)
Selectable
SSCK (I/O): Clock I/O pin
SSI (I/O): Data I/O pin
SSO (I/O): Data I/O pin
SCS (I/O): Chip-select I/O pin
• When the MSS bit in the SSCRH register is set to 0 (operates as slave device),
• When the MSS bit in the SSCRH register is set to 1 (operates as master
• Clock polarity and phase of SSCK can be selected.
• Overrun error
• Conflict error
overrun error, and conflict error).
• SSCK clock polarity
• SSCK clock phase
• SSI pin select function
• Transfer data length: 8 bits
5 interrupt requests (transmit-end, transmit-data-empty, receive-data-full,
• Data transfer direction
external clock is selected (input from SSCK pin).
device), internal clock (selectable among f1/256, f1/128, f1/64, f1/32, f1/16, f1/8
and f1/4, output from SSCK pin) is selected.
Continuous transmission and reception of serial data are supported since both
transmitter and receiver have buffer structures.
Overrun error occurs during reception and completes in error. While the RDRF
bit in the SSSR register is set to 1 (data in the SSRDR register) and when next
serial data receive is completed, the ORER bit is set to 1.
When the SSUMS bit in the SSMR2 register is set to 1 (4-wire bus
communication mode) and the MSS bit in the SSCRH register is set to 1
(operates as master device) and when starting a serial communication, the CE
bit in the SSSR register is set to 1 if “L” applies to the SCS pin input. When the
SSUMS bit in the SSMR2 register is set to 1 (4-wire bus communication
mode), the MSS bit in the SSCRH register is set to 0 (operates as slave
device) and the SCS pin input changes state from “L” to “H”, the CE bit in the
SSSR register is set to 1.
Selects MSB-first or LSB-first
Selects “L” or “H” level when clock stops
Selects edge of data change and data download
The SSISEL bit in the PMR register can select P3_3 or P1_6 as SSI pin.
(1)
Specification
16. Clock Synchronous Serial Interface

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