MC908AP32ACFBE Freescale Semiconductor, MC908AP32ACFBE Datasheet
MC908AP32ACFBE
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MC68HC908AP64A MC68HC908AP32A MC68HC908AP16A MC68HC908AP8A Data Sheet M68HC08 Microcontrollers MC68HC908AP64A Rev. 3 10/2007 freescale.com ...
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...
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... The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash® technology licensed from SST. ...
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... Registers, corrected COCO bit description. Introduction, added unused pin information. (BRK), updated functional details. Characteristics, updated stop I — Changed “The ADC clock should MC68HC908AP A-Family Data Sheet, Rev. 3 Page Number(s) — values. DD 250 — Freescale Semiconductor ...
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... Chapter 18 Keyboard Interrupt Module (KBI .275 Chapter 19 Computer Operating Properly (COP .281 Chapter 20 Low-Voltage Inhibit (LVI .285 Chapter 21 Break Module (BRK .289 Chapter 22 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295 Chapter 23 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .309 Chapter 24 Ordering Information .313 Freescale Semiconductor MC68HC908AP A-Family Data Sheet, Rev ...
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... List of Chapters 6 MC68HC908AP A-Family Data Sheet, Rev. 3 Freescale Semiconductor ...
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... Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.3 Configuration Register 1 (CONFIG1 3.4 Configuration Register 2 (CONFIG2 3.5 Mask Option Register (MOR 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.3 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 4.3.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Freescale Semiconductor Chapter 1 General Description , DDA SS SSA Chapter 2 Memory Chapter 3 Chapter 4 Central Processor Unit (CPU) MC68HC908AP A-Family Data Sheet, Rev. 3 ...
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... Acquisition and Tracking Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.3.5 Manual and Automatic PLL Bandwidth Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 6.3.6 Programming the PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 6.3.7 Special Programming Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.3.8 Base Clock Selector Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 8 Chapter 5 Oscillator (OSC) Chapter 6 Clock Generator Module (CGM) MC68HC908AP A-Family Data Sheet, Rev. 3 Freescale Semiconductor ...
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... SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 7.4.1 SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 7.4.2 SIM Counter During Stop Mode Recovery 103 7.4.3 SIM Counter and Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 7.5 Exception Control 104 Freescale Semiconductor ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 DDA ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 SSA Chapter 7 System Integration Module (SIM) MC68HC908AP A-Family Data Sheet, Rev ...
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... Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 9.4.1 TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 9.4.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 9.4.3 Output Compare 134 9.4.3.1 Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 9.4.3.2 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 10 Chapter 8 Monitor Mode (MON) Chapter 9 Timer Interface Module (TIM) MC68HC908AP A-Family Data Sheet, Rev. 3 Freescale Semiconductor ...
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... Break Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 11.4.2.4 Idle Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 11.4.2.5 Inversion of Transmitted Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 11.4.2.6 Transmitter Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 11.4.3 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 11.4.3.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 11.4.3.2 Character Reception 156 11.4.3.3 Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Freescale Semiconductor Chapter 10 Timebase Module (TBM) Chapter 11 MC68HC908AP A-Family Data Sheet, Rev ...
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... Character Reception 187 12.5.3.3 Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 12.5.3.4 Framing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 12.5.3.5 Baud Rate Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 12.5.3.6 Receiver Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 12.5.3.7 Receiver Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 12.5.3.8 Error Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 12.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 12 Chapter 12 MC68HC908AP A-Family Data Sheet, Rev. 3 Freescale Semiconductor ...
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... I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 13.12.1 MISO (Master In/Slave Out 220 13.12.2 MOSI (Master Out/Slave In 220 13.12.3 SPSCK (Serial Clock 220 13.12.4 SS (Slave Select 221 13.12.5 CGND (Clock Ground 222 13.13 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 Freescale Semiconductor Chapter 13 MC68HC908AP A-Family Data Sheet, Rev ...
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... Block Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 14.9 SMBus Protocol Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 15.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 15.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 15.3.1 ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 14 Chapter 14 Multi-Master IIC Interface (MMIIC) Chapter 15 Analog-to-Digital Converter (ADC) MC68HC908AP A-Family Data Sheet, Rev. 3 Freescale Semiconductor ...
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... Port D Data Register (PTD 266 16.5.2 Data Direction Register D (DDRD 267 17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 17.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 17.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 17.4 IRQ1 and IRQ2 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 Freescale Semiconductor ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 DDA ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 SSA ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 REFH ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 REFL Chapter 16 Input/Output (I/O) Ports ...
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... Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 19.8 COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 20.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 20.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 20.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 16 Chapter 18 Keyboard Interrupt Module (KBI) Chapter 19 Computer Operating Properly (COP) Chapter 20 Low-Voltage Inhibit (LVI) MC68HC908AP A-Family Data Sheet, Rev. 3 Freescale Semiconductor ...
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... Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 22.8 5V ADC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 22.9 MMIIC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 22.10 CGM Electrical Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 22.11 5V SPI Characteristics 304 22.12 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 Freescale Semiconductor Chapter 21 Break Module (BRK) Chapter 22 Electrical Specifications MC68HC908AP A-Family Data Sheet, Rev ...
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... Low-Profile Quad Flat Pack (LQFP 310 23.3 44-Pin Quad Flat Pack (QFP 311 23.4 42-Pin Shrink Dual In-Line Package (SDIP 312 24.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 24.2 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 18 Chapter 23 Mechanical Specifications Chapter 24 Ordering Information MC68HC908AP A-Family Data Sheet, Rev. 3 Freescale Semiconductor ...
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... Two 16-bit, 2-channel timer interface modules (TIM1 and TIM2) with selectable input capture, output compare, and PWM capability on each channel 1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. Freescale Semiconductor RAM Size (bytes) 2,048 ...
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... Fast 8 × 8 multiply instruction • • Fast 16/8 divide instruction • Binary-coded decimal (BCD) instructions • Optimization for controller applications • Efficient C language support 1.3 MCU Block Diagram Figure 1-1 shows the structure of the MC68HC908AP64A. 20 MC68HC908AP A-Family Data Sheet, Rev. 3 Freescale Semiconductor ...
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... POWER-ON RESET MODULE VDD VDDA VSS POWER VSSA VREG VREFH ADC REFERENCE VREFL Figure 1-1. MC68HC908AP64A Block Diagram Freescale Semiconductor INTERNAL BUS 10-BIT ANALOG-TO-DIGITAL CONVERTER MODULE TIMEBASE MODULE 2-CHANNEL TIMER INTERFACE MODULE 1 2-CHANNEL TIMER INTERFACE MODULE 2 SERIAL COMMUNICATIONS INTERFACE MODULE 1 MULTI-MASTER IIC (SMBUS) ...
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... Pin Assignment PTB6/T2CH0 1 2 VREG 3 PTB5/T1CH1 VDD 4 5 OSC1 6 OSC2 VSS 7 8 PTB4/T1CH0 IRQ1 9 PTB3/RxD 10 RST 11 PTB2/TxD 12 NC: No connection Figure 1-2. 48-Pin LQFP Pin Assignments 22 MC68HC908AP A-Family Data Sheet, Rev. 3 VREFH 36 35 VREFL PTA0/ADC0 PTA1/ADC1 29 PTA2/ADC2 28 PTA3/ADC3 27 PTA4/ADC4 26 PTA5/ADC5 PTA6/ADC6 25 Freescale Semiconductor ...
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... PTB6/T2CH0 1 VREG 2 PTB5/T1CH1 3 VDD 4 OSC1 5 OSC2 6 VSS 7 PTB4/T1CH0 8 IRQ1 9 PTB3/RxD 10 RST 11 Figure 1-3. 44-Pin QFP Pin Assignments Freescale Semiconductor MC68HC908AP A-Family Data Sheet, Rev. 3 Pin Assignment PTD7/KBI7 33 32 VREFH 31 VREFL 30 PTA0/ADC0 29 PTA1/ADC1 28 PTA2/ADC2 PTA3/ADC3 27 PTA4/ADC4 26 25 PTA5/ADC5 PTA6/ADC6 24 PTA7/ADC7 23 23 ...
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... PTC0/IRQ2 PTC1 Figure 1-4. 42-Pin SDIP Pin Assignment MC68HC908AP A-Family Data Sheet, Rev. 3 VDDA 42 VSSA 41 PTD3/KBI3 40 PTD4/KBI4 39 PTD5/KBI5 38 PTD6/KBI6 37 PTD7/KBI7 36 VREFH 35 VREFL 34 33 PTA0/ADC0 PTA1/ADC1 32 31 PTA2/ADC2 PTA3/ADC3 30 29 PTA4/ADC4 28 PTA5/ADC5 27 PTA6/ADC6 26 PTA7/ADC7 25 PTC2/MISO 24 PTC3/MOSI 23 PTC4/SS 22 PTC5/SPSCK Unconnected Unconnected Freescale Semiconductor ...
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... CGM external filter capacitor connection. CGMXFC 8-bit general purpose I/O port. PTA0/ADC0 Pins as ADC inputs, ADC0–ADC7. : PTA7/ADC7 Each pin has high current sink for LED. Freescale Semiconductor Table 1-2. Table 1-2. Pin Functions PIN DESCRIPTION MC68HC908AP A-Family Data Sheet, Rev. 3 Pin Functions VOLTAGE ...
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... Table 1-2. Pin Functions PIN DESCRIPTION for V tolerance. REG , C BYPASS BULK MC68HC908AP A-Family Data Sheet, Rev. 3 VOLTAGE IN/OUT LEVEL V In/Out V In/Out V In/Out V Out In/Out V In/Out V In/Out V In/Out V In/Out Out In/Out V Out In/Out In Figure 1-5 are optional bulk current bypass Freescale Semiconductor ...
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... All internal logics, except for the I/O pads, are powered by REG V output. V requires an external ceramic bypass capacitor of 100 nF as REG REG the bypass capacitor as close to the V Figure 1-6. Regulator Power Supply Bypassing Freescale Semiconductor DDA C1(a) 0.1 µF + C2(a) ...
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... General Description 28 MC68HC908AP A-Family Data Sheet, Rev. 3 Freescale Semiconductor ...
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... COP control register, COPCTL 2.3 Monitor ROM The 959 bytes at addresses $FC00–$FDFF and $FE10–$FFCE are reserved ROM addresses that contain the instructions for the monitor functions. (See Freescale Semiconductor Chapter 8 Monitor Mode MC68HC908AP A-Family Data Sheet, Rev. 3 Figure 2-1, includes: (MON) ...
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... RAM 1,024 Bytes 1,024 Bytes $045F Unimplemented Unimplemented 1,024 Bytes 1,024 Bytes $0860 FLASH Memory 8,192 Bytes FLASH Memory ↓ 16,384 Bytes $485F $4860 Unimplemented 54,176 Bytes Unimplemented ↓ 45,984 Bytes $FBFF Freescale Semiconductor $0060 $045F $0860 $285F $2860 ↓ $FBFF ...
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... Reset: Read: $000B Unimplemented Write: Reset: Read: Port-A LED Control $000C Register Write: (LEDA) Reset Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet Freescale Semiconductor Bit PTA7 PTA6 PTA5 PTA4 Unaffected by reset PTB7 PTB6 PTB5 PTB4 Unaffected by reset PTC7 PTC6 ...
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... SCRF IDLE Unaffected by reset 0 0 SCP1 SCP0 Indeterminate = Unimplemented MC68HC908AP A-Family Data Sheet, Rev CPHA SPWOM SPE SPTE MODFEN SPR1 WAKE ILTY PEN RWU ORIE NEIE FEIE BKF SCR2 SCR1 Reserved Freescale Semiconductor Bit 0 SPTIE 0 SPR0 PTY 0 SBK 0 PEIE RPF SCR0 0 ...
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... High Write: (T1MODH) Reset: Read: Timer 1 Counter Modulo $0024 Register Low Write: (T1MODL) Reset: Read: Timer 1 Channel 0 Status and $0025 Write: Control Register (T1SC0) Reset Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet Freescale Semiconductor Bit KBIE7 KBIE6 KBIE5 KBIE4 ...
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... Indeterminate after reset Bit Indeterminate after reset X = Indeterminate = Unimplemented MC68HC908AP A-Family Data Sheet, Rev ELS1B ELS1A TOV1 PS2 PS1 ELS0B ELS0A TOV0 Reserved Freescale Semiconductor Bit 0 Bit 8 Bit 0 CH1MAX 0 Bit 8 Bit 0 PS0 0 Bit 8 0 Bit 0 0 Bit 8 1 Bit 0 1 CH0MAX 0 Bit 8 Bit 0 ...
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... Unimplemented Write: Reset: Read: $003D Unimplemented Write: Reset: Read: $003E Unimplemented Write: Reset: Read: $003F Unimplemented Write: Reset Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet Freescale Semiconductor Bit CH1F 0 CH1IE MS1A Bit Indeterminate after reset Bit Indeterminate after reset ...
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... WAKE ILTY PEN RWU ORIE NEIE FEIE BKF SCR2 SCR1 TNP1 TNP0 MMAD3 MMAD2 MMAD1 MMCRCBY MMTXAK REPSEN MMRW MMRXAK MMCRCBF MMTXBE MMTD3 MMTD2 MMTD1 Reserved Freescale Semiconductor Bit 0 PTY 0 SBK 0 PEIE RPF SCR0 0 IREN 0 MMEXTAD MMCRCEF Unaffected MMRXBF 0 MMTD0 0 ...
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... ADC Status and Control $0057 Register Write: (ADSCR) Reset: Read: ADC Clock Control Register $0058 Write: (ADICLK) Reset: Read: ADC Data Register High 0 $0059 Write: (ADRH0) Reset Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet Freescale Semiconductor Bit MMRD7 MMRD6 MMRD5 MMRD4 ...
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... MC68HC908AP A-Family Data Sheet, Rev ADx ADx ADx AD5 AD4 AD3 AD5 AD4 AD3 AD5 AD4 AD3 AUTO1 AUTO0 SBSW R R Note 0 ILAD MODRST LVI IF2 IF1 IF10 IF9 IF8 Reserved Freescale Semiconductor Bit 0 ADx R 0 AD2 R 0 AD2 R 0 AD2 R 0 ASCAN IF7 R 0 ...
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... Read: Write: Read: Mask Option Register $FFCF Write: # (MOR) Erased: Reset: Read: COP Control Register $FFFF Write: (COPCTL) Reset: # MOR is a non-volatile FLASH register; write by programming Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet Freescale Semiconductor Bit IF21 IF20 IF19 ...
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... SCI Error Vector (High) IF11 $FFE7 SCI Error Vector (Low) $FFE8 MMIIC Interrupt Vector (High) IF10 $FFE9 MMIIC Interrupt Vector (Low) $FFEA TIM2 Overflow Vector (High) IF9 $FFEB TIM2 Overflow Vector (Low) MC68HC908AP A-Family Data Sheet, Rev. 3 Vector Freescale Semiconductor ...
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... RAM locations can be used for I/O control and user data or code. When the stack pointer is moved from its reset location at $00FF, direct addressing mode instructions can access efficiently all page zero RAM locations. Page zero RAM, therefore, provides ideal locations for frequently accessed global variables. Freescale Semiconductor Address $FFEC TIM2 Channel 1 Vector (High) ...
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... No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. 42 NOTE NOTE FLASH Memory Size (Bytes) 62,368 32,768 16,384 8,192 NOTE MC68HC908AP A-Family Data Sheet, Rev. 3 Memory Address Range $0860–$FBFF $0860–$885F $0860–$485F $0860–$285F (1) Freescale Semiconductor ...
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... Set the ERASE bit and clear the MASS bit in the FLASH control register. 2. Write any data to any FLASH location within the page address range desired. (5 µs). 3. Wait for a time, t nvs 4. Set the HVEN bit. 5. Wait for a time t (20 ms). erase 6. Clear the ERASE bit. (5 µs). 7. Wait for a time, t nvh Freescale Semiconductor HVEN MC68HC908AP A-Family Data Sheet, Rev ...
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... Wait for time, t prog 8. Repeat steps 6 and 7 until all bytes within the row are programmed. 9. Clear the PGM bit. (5 µs). 10. Wait for time, t nvh 11. Clear the HVEN bit. 44 NOTE NOTE shows a flowchart of the programming algorithm.) MC68HC908AP A-Family Data Sheet, Rev. 3 Freescale Semiconductor ...
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... The mask option register ($FFCF) and the 48 bytes of user interrupt vectors ($FFD0–$FFFF) are always protected, regardless of the value in the FLASH block protect register. A mass erase is required to erase these locations. Freescale Semiconductor NOTE NOTE NOTE MC68HC908AP A-Family Data Sheet, Rev. 3 ...
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... Write data to the FLASH address to be programmed 7 Wait for a time, t Completed programming this row? N MC68HC908AP A-Family Data Sheet, Rev. 3 nvs pgs prog Y 9 Clear PGM bit 10 Wait for a time, t nvh 11 Clear HVEN bit 12 Wait for a time, t rcv End of Programming Freescale Semiconductor ...
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... Except for the mask option register ($FFCF) and the 48-byte user vectors ($FFD0–$FFFF). These FLASH locations are always protected. Freescale Semiconductor BPR6 BPR5 BPR4 BPR3 0 0 ...
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... Memory 48 MC68HC908AP A-Family Data Sheet, Rev. 3 Freescale Semiconductor ...
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... Reset: Mask-Option-Register Read: # $FFCF Write: (MOR) Erased: † One-time writable register after each reset. # MOR is a non-volatile FLASH register; write by programming. Figure 3-1. CONFIG and MOR Registers Summary Freescale Semiconductor DD Bit STOP_ STOP_ STOP_ OSCCLK1 OSCCLK0 ICLKDIS RCLKEN XCLKEN 0 0 ...
Page 50
... LVIRSTD disables the reset signal from the LVI module. (See 1 = LVI module resets disabled 0 = LVI module resets enabled 50 NOTE 3- LVISTOP LVIRSTD LVIPWRD LVIREGD Chapter 20 Low-Voltage Inhibit NOTE MC68HC908AP A-Family Data Sheet, Rev Bit 0 SSREC STOP COPD Chapter 19 Computer Operating (LVI).) Chapter 20 Low-Voltage Inhibit Freescale Semiconductor (LVI).) ...
Page 51
... STOP instruction enabled 0 = STOP instruction treated as illegal opcode COPD — COP Disable Bit COPD disables the COP module. (See 1 = COP module disabled 0 = COP module enabled Freescale Semiconductor LVI circuit. (See Chapter 20 Low-Voltage Inhibit LVI circuit. (See Chapter 20 Low-Voltage Inhibit NOTE NOTE Chapter 19 Computer Operating Properly MC68HC908AP A-Family Data Sheet, Rev ...
Page 52
... Reset clears these two bits. OSCCLK1 STOP_ STOP_ OSCCLK1 OSCCLK0 RCLKEN XCLKEN Chapter 5 Oscillator OSCCLK0 MC68HC908AP A-Family Data Sheet, Rev Bit SCIBD- SRC (OSC).) Timebase Clock Source Internal oscillator (ICLK) RC oscillator (RCCLK) X-tal oscillator (XTAL) Not used Freescale Semiconductor ...
Page 53
... These bits are unaffected by reset. (See Bits 5–0 — Should be left as 1’s OSCSEL1 OSCSEL0 The internal oscillator is a free running oscillator and is available after each POR or reset turned-off in stop mode by setting the STOP_ICLKDIS bit in CONFIG2. Freescale Semiconductor , is used as clock source for SCI BUS Unaffected by reset Reserved Table 3-1 ...
Page 54
... Configuration & Mask Option Registers (CONFIG & MOR) 54 MC68HC908AP A-Family Data Sheet, Rev. 3 Freescale Semiconductor ...
Page 55
... Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions • Enhanced binary-coded decimal (BCD) data handling • Modular architecture with expandable internal bus definition for extension of addressing range beyond 64 Kbytes • Low-power stop and wait modes Freescale Semiconductor MC68HC908AP A-Family Data Sheet, Rev ...
Page 56
... STACK POINTER (SP) 0 PROGRAM COUNTER (PC CONDITION CODE REGISTER (CCR) CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO’S COMPLEMENT OVERFLOW FLAG Figure 4-1. CPU Registers Unaffected by reset Figure 4-2. Accumulator (A) MC68HC908AP A-Family Data Sheet, Rev Bit 0 Freescale Semiconductor ...
Page 57
... During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF. The vector address is the address of the first instruction to be executed after exiting the reset state. Freescale Semiconductor 13 12 ...
Page 58
... If the interrupt service routine modifies H, then the user must stack and unstack H using the PSHH and PULH instructions Loaded with Vector from $FFFE and $FFFF Figure 4-5. Program Counter (PC NOTE MC68HC908AP A-Family Data Sheet, Rev Bit Bit Freescale Semiconductor ...
Page 59
... I bit remains clear. After exit by reset, the I bit is set. • Disables the CPU clock After exiting stop mode, the CPU clock begins running after the oscillator stabilization delay. Freescale Semiconductor MC68HC908AP A-Family Data Sheet, Rev. 3 Arithmetic/Logic Unit (ALU) 59 ...
Page 60
... SP1 9EE9 ff SP2 9ED9 ee ff IMM AB ii DIR BB dd EXT IX2 ↕ ↕ – ↕ ↕ ↕ IX1 SP1 9EEB ff SP2 9EDB ee ff – – – – – – IMM A7 ii – – – – – – IMM AF ii Freescale Semiconductor ...
Page 61
... BHCS rel Branch if Half Carry Bit Set BHI rel Branch if Higher Branch if Higher or Same BHS rel (Same as BCC) BIH rel Branch if IRQ Pin High BIL rel Branch if IRQ Pin Low Freescale Semiconductor Table 4-1. Instruction Set Summary Description A ← (A) & ( ← (PC rel ? ( ← ...
Page 62
... DIR (b6 DIR (b7 – – – – – – REL 21 rr DIR (b0 DIR (b1 DIR (b2 DIR (b3 – – – – – ↕ DIR (b4 DIR (b5 DIR (b6 DIR (b7 DIR (b0 DIR (b1 DIR (b2 DIR (b3 – – – – – – DIR (b4 DIR (b5 DIR (b6 DIR (b7 Freescale Semiconductor ...
Page 63
... CPX ,X Compare X with M CPX opr,X CPX opr,X CPX opr,SP CPX opr,SP DAA Decimal Adjust A Freescale Semiconductor Table 4-1. Instruction Set Summary Description PC ← (PC push (PCL) SP ← (SP) – 1; push (PCH) SP ← (SP) – ← (PC) + rel PC ← (PC rel ? (A) – (M) = $00 PC ← (PC rel ? (A) – (M) = $00 PC ← ...
Page 64
... IX2 IX1 DIR BD dd EXT – – – – – – IX2 IX1 IMM A6 ii DIR B6 dd EXT IX2 – – ↕ ↕ – IX1 SP1 9EE6 ff SP2 9ED6 ee ff IMM – – ↕ ↕ – DIR 55 dd Freescale Semiconductor ...
Page 65
... ORA opr ORA opr,X Inclusive OR A and M ORA opr,X ORA ,X ORA opr,SP ORA opr,SP PSHA Push A onto Stack PSHH Push H onto Stack PSHX Push X onto Stack PULA Pull A from Stack Freescale Semiconductor Table 4-1. Instruction Set Summary Description X ← ( ← (M) (M) Destination Source H:X ← ...
Page 66
... INH 99 – – 1 – – – INH 9B DIR B7 dd EXT IX2 – – ↕ ↕ – IX1 SP1 9EE7 ff SP2 9ED7 – – ↕ ↕ – DIR 35 dd – – 0 – – – INH 8E Freescale Semiconductor ...
Page 67
... TSX Transfer SP to H:X TXA Transfer TXS Transfer H WAIT Enable Interrupts; Wait for Interrupt Freescale Semiconductor Table 4-1. Instruction Set Summary Description M ← (X) A ← (A) – (M) PC ← (PC Push (PCL) SP ← (SP) – 1; Push (PCH) SP ← (SP) – 1; Push (X) SP ← (SP) – 1; Push (A) SP ← ...
Page 68
... Stack pointer 16-bit offset addressing mode Stack pointer Undefined Overflow bit Index register low byte Zero bit Logical AND Logical OR Logical EXCLUSIVE OR Contents of Negation (two’s complement) Immediate value Sign extend Loaded with If Concatenated with Set or cleared Not affected Freescale Semiconductor ...
Page 69
Bit Manipulation Branch Read-Modify-Write DIR DIR REL DIR INH MSB LSB BRSET0 BSET0 BRA NEG NEGA NEGX 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 5 ...
Page 70
... Central Processor Unit (CPU) 70 MC68HC908AP A-Family Data Sheet, Rev. 3 Freescale Semiconductor ...
Page 71
... CGMXCLK and CGMRCLK — Reference clock for clock generator module (CGM) and other MCU sub-systems other than TBM and COP. This is the main reference clock for the MCU. • OSCCLK — Reference clock for timebase module (TBM). Freescale Semiconductor NOTE MC68HC908AP A-Family Data Sheet, Rev. 3 regulator, ...
Page 72
... Figure 5-2. Mask Option Register (MOR CGM PLL CGMXCLK CGMRCLK MUX XCLK RCCLK RC OSCILLATOR BUS CLOCK OSC2 (MOR Unaffected by reset Reserved MC68HC908AP A-Family Data Sheet, Rev TBM OSCCLK CONFIG2 OSCCLK1 MUX OSCCLK0 SIM (and COP) ICLK INTERNAL OSCILLATOR From SIM 2 1 Bit Freescale Semiconductor ...
Page 73
... Figure 5-3. Configuration Register 2 (CONFIG2) Table 5-2. Timebase Module Reference Clock Selection OSCCLK1 The RCCLK or XCLK is only available if that clock is selected as the CGM reference clock, whereas the ICLK is always available. Freescale Semiconductor Table 5-1. CGMXCLK Clock Selection CGMXCLK OSC2 Pin — — Not used f ICLK Internal oscillator generates the CGMXCLK ...
Page 74
... CONFIG2 STOP_ICLKDIS MCU free running clock that requires no ICLK From SIM To Clock Selection MUX and COP SIMOSCEN ICLK EN INTERNAL OSCILLATOR Figure 5-4. Internal Oscillator MC68HC908AP A-Family Data Sheet, Rev. 3 From SIM BUS CLOCK OSC2 Freescale Semiconductor ...
Page 75
... Fixed capacitor • Tuning capacitor, C (can also be a fixed capacitor) 2 • Feedback resistor • Series resistor, R (optional) S Freescale Semiconductor To Clock Selection MUX SIMOSCEN RCCLK EN RC OSCILLATOR OSC1 V REG R C EXT Figure 5-5. RC Oscillator MC68HC908AP A-Family Data Sheet, Rev Oscillator From SIM ...
Page 76
... Oscillator Enable Signal (SIMOSCEN) The SIMOSCEN signal from the system integration module (SIM) enables/disables the x-tal oscillator, the RC-oscillator, or the internal oscillator circuit. 76 SIMOSCEN OSC1 1–8MHz C 1 Figure 5-6. Crystal Oscillator MC68HC908AP A-Family Data Sheet, Rev Clock Selection MUX XCLK OSC2 Freescale Semiconductor ...
Page 77
... The internal oscillator clock continues operation in stop mode. It can be disabled by setting the STOP_ICLKDIS bit to logic 1 before entering stop mode. 5.8 Oscillator During Break Mode The oscillator continues to drive CGMXCLK when the device enters the break state. Freescale Semiconductor MC68HC908AP A-Family Data Sheet, Rev. 3 Low Power Modes Chapter 10 Timebase Module ...
Page 78
... Oscillator (OSC) 78 MC68HC908AP A-Family Data Sheet, Rev. 3 Freescale Semiconductor ...
Page 79
... VCO clock, CGMPCLK, divided by two as the base clock, CGMOUT. The SIM derives the system clocks from either CGMOUT or CGMXCLK. Figure 6-1 shows the structure of the CGM. Figure 6 summary of the CGM registers. Freescale Semiconductor MC68HC908AP A-Family Data Sheet, Rev ...
Page 80
... AUTO ACQ PLLIE PLLF PRE[1: CGMVCLK FREQUENCY DIVIDER Figure 6-1. CGM Block Diagram MC68HC908AP A-Family Data Sheet, Rev SIM (and COP) To Timebase Module (TBM) To ADC A CLOCK ÷ SELECT CIRCUIT *WHEN CGMOUT = CGMPCLK Freescale Semiconductor CGMOUT To SIM SIMDIV2 From SIM CGMINT To SIM ...
Page 81
... The PLL can change between acquisition and tracking modes either automatically or manually. 6.3.3 PLL Circuits The PLL consists of these circuits: • Voltage-controlled oscillator (VCO) • Reference divider • Frequency pre-scaler • Modulo VCO frequency divider Freescale Semiconductor Bit PLLF PLLIE PLLON LOCK AUTO ...
Page 82
... Modes. The value of the external capacitor and the 6.5.2 PLL Bandwidth Control 6.3.8 Base Clock Selector MC68HC908AP A-Family Data Sheet, Rev Modulating the voltage on the is equal to the nominal VRS RCLK , is fed back through a programmable /(N × VDV VCLK Register.) Circuit.) The PLL is automatically in Freescale Semiconductor (See ...
Page 83
... Programming the PLL The following procedure shows how to program the PLL. The round function in the following equations means that the real number should be rounded to the nearest integer number. Freescale Semiconductor Register read-only indicator of the mode of Modes.) 6.8 Acquisition/Lock Time Specifications 6 ...
Page 84
... MC68HC908AP A-Family Data Sheet, Rev and then VCLKDES × f BUS /R. For stability and lock time reduction, RCLK ) to a value determined RCLK Chapter 22 Electrical to an integer divisor of f RCLK ⎛ ⎞ f ⎫ VCLKDES ⎜ ⎟ ⎬ ------------------------- - f ⎝ ⎠ ⎭ RCLK and f . VCLK BUS ) Freescale Semiconductor , is , BUSDES ...
Page 85
... In the PLL reference divider select register (PMDS), program the binary coded equivalent of R. The values for and R can only be programmed when the PLL is off (PLLON = 0). Table 6-1 provides numeric examples (numbers are in hexadecimal notation): Freescale Semiconductor Frequency Range 0 < f < 9,830,400 VCLK 9,830,400 ≤ f < ...
Page 86
... MHz 2 MHz 8.0 MHz 4 MHz 4.0 MHz 4 MHz 8.0 MHz 8 MHz 4.0 MHz 8 MHz 7.3728 MHz 4.9152 MHz 4.9152 MHz 4.9152 MHz 6.3.6 Programming the PLL Circuit.) MC68HC908AP A-Family Data Sheet, Rev does not account for three possible Freescale Semiconductor ...
Page 87
... PLL Analog Ground Pin ( ground pin used by the analog portions of the PLL. Connect the V SSA potential as the V pin. SS Freescale Semiconductor for routing information, filter network and its effects on PLL CGMXFC 1 kΩ 0.22 µF Figure 6-3. CGM External Connections 6-3.) ...
Page 88
... PLL Multiplier Select • PLL VCO range select register (PMRS) (See 6.5.4 PLL VCO Range Select • PLL reference divider select register (PMDS) (See 6.5.5 PLL Reference Divider Select 88 NOTE Register.) Registers.) Register.) Register.) MC68HC908AP A-Family Data Sheet, Rev. 3 Freescale Semiconductor ...
Page 89
... CGMXCLK and three CGMPCLK cycles to complete the transition from one source clock to the other. During the transition, CGMOUT is held in stasis. (See Selector Circuit.) Reset clears the BCS bit CGMPCLK divided by two drives CGMOUT 0 = CGMXCLK divided by two drives CGMOUT Freescale Semiconductor PLLF ...
Page 90
... NOTE: Do not program value NOTE Circuit.) PLL.) PRE1 and PRE0 cannot be written when the 6.3.6 Programming the PLL, and VRS MC68HC908AP A-Family Data Sheet, Rev. 3 Prescaler Multiplier 6.5.4 PLL VCO Range Select . VPR1:VPR0 cannot be written when VCO Power-of-Two Range Multiplier Freescale Semiconductor ...
Page 91
... When the AUTO bit is clear, ACQ is a read/write bit that controls whether the PLL is in acquisition or tracking mode. In automatic bandwidth control mode (AUTO = 1), the last-written value from manual operation is stored in a temporary location and is recovered when manual operation resumes. Reset clears this bit, enabling acquisition mode Tracking mode 0 = Acquisition mode Freescale Semiconductor LOCK 0 ...
Page 92
... VRS[7:0] cannot be written when the PLLON bit in the VRS Exceptions.) A value of $00 in the VCO range select MC68HC908AP A-Family Data Sheet, Rev Bit 0 MUL10 MUL9 MUL8 Bit 0 MUL2 MUL1 MUL0 Bit 0 VRS2 VRS1 VRS0 6.5.1 PLL Control Register.), controls the Freescale Semiconductor ...
Page 93
... When the PLL enters lock, the divided VCO clock, CGMPCLK, divided by two can be selected as the CGMOUT source by setting BCS in the PCTL. When the PLL exits lock, the Freescale Semiconductor Exceptions.). Reset initializes the register to NOTE ...
Page 94
... To protect the PLLF bit during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), software can read and write the PLL control register during the break state without affecting the PLLF bit. 94 NOTE 7.7.3 SIM Break Flag Control MC68HC908AP A-Family Data Sheet, Rev. 3 Register.) Freescale Semiconductor ...
Page 95
... PLL. A fixed value is best. Variable supplies, such as batteries, are acceptable if they vary within a known range at very slow speeds. Noise on the power supply is not acceptable, because it causes small frequency errors which continually change the acquisition time of the PLL. Freescale Semiconductor 6.3.3 PLL Circuits, Register ...
Page 96
... Time, the external filter network is critical to the is recommended when using a 4MHz reference clock CGMXFC 1 kΩ SSA (a) Figure 6-10. PLL Filter MC68HC908AP A-Family Data Sheet, Rev. 3 Figure 6-10 (b) is used in CGMXFC 0.22 µF V SSA (b) Freescale Semiconductor ...
Page 97
... Internal address bus IDB Internal data bus PORRST Signal from the power-on reset module to the SIM IRST Internal reset signal R/W Read/write signal Freescale Semiconductor Figure 7-1. Table 7-1. Signal Name Conventions Description MC68HC908AP A-Family Data Sheet, Rev. 3 Figure 7 summary of the SIM 97 ...
Page 98
... ICLK (FROM OSC) CGMOUT (FROM CGM) INTERNAL CLOCKS LVI (FROM LVI MODULE) ILLEGAL OPCODE (FROM CPU) ILLEGAL ADDRESS (FROM ADDRESS MAP DECODERS) COP (FROM COP MODULE) INTERRUPT SOURCES CPU INTERFACE SBSW NOTE ILAD MODRST LVI IF3 IF2 IF1 Freescale Semiconductor Bit ...
Page 99
... OSC1 STOP MODE CLOCK ENABLE SIGNALS FROM CONFIG2 CGMRCLK PHASE-LOCKED LOOP (PLL) 7.2.1 Bus Timing In user mode, the internal bus frequency is either the oscillator output (CGMXCLK) divided by four or the divided PLL output (CGMPCLK) divided by four. Freescale Semiconductor IF14 IF13 IF12 IF11 ...
Page 100
... POR/LVI All others 100 7.6.2 Stop Mode.) 7.4 SIM Counter), but an external reset does not. Each of Table 7-2. Reset Recovery Actual Number of Cycles 4163 (4096 + ( MC68HC908AP A-Family Data Sheet, Rev. 3 7.7 SIM Registers.) Table 7-2 for details. Figure 7-4 Freescale Semiconductor ...
Page 101
... The external reset pin (RST) is held low while the SIM counter counts out 4096 + 32 ICLK cycles. Thirty-two ICLK cycles later, the CPU and memories are released from reset to allow the reset vector sequence to occur. Freescale Semiconductor Figure 7-4. External Reset Timing NOTE ...
Page 102
... SIM reset status register (SRSR) and causes a reset. 102 32 32 CYCLES CYCLES Figure 7-7. POR Recovery on the RST pin disables the COP module. TST MC68HC908AP A-Family Data Sheet, Rev. 3 $FFFE $FFFF while the MCU is in monitor TST Freescale Semiconductor ...
Page 103
... CGMXCLK cycles down to 32 CGMXCLK cycles. This is ideal for applications using canned oscillators that do not require long start-up times from stop mode. External crystal applications should use the full stop recovery time, that is, with SSREC cleared. Freescale Semiconductor Chapter 8 Monitor Mode MC68HC908AP A-Family Data Sheet, Rev. 3 ...
Page 104
... SP – 1 CCR – 1[15:8] PC – 1[7:0] Figure 7-9. Interrupt Recovery Timing MC68HC908AP A-Family Data Sheet, Rev. 3 for details.) The SIM counter is for counter control and Figure 7-8 shows VECT H VECT L START ADDR CCR V DATA H V DATA L OPCODE OPCODE OPERAND Freescale Semiconductor ...
Page 105
... If more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is serviced first. Figure 7-11 demonstrates what happens when two interrupts are pending interrupt is pending upon exit from the original interrupt service routine, the pending interrupt is serviced before the LDA instruction is executed. Freescale Semiconductor FROM RESET BREAK I BIT SET? YES INTERRUPT? ...
Page 106
... The interrupt status registers can be useful for debugging. 106 CLI LDA #$FF PSHH INT1 INTERRUPT SERVICE ROUTINE PULH RTI PSHH INT2 INTERRUPT SERVICE ROUTINE PULH RTI . Interrupt Recognition Example NOTE NOTE MC68HC908AP A-Family Data Sheet, Rev. 3 BACKGROUND ROUTINE Table 7-3 summarizes the Freescale Semiconductor ...
Page 107
... Bit 7 Read: 0 Write: R Reset Figure 7-14. Interrupt Status Register 3 (INT3) IF21–IF15 — Interrupt Flags 21–15 These flags indicate the presence of an interrupt request from the source shown Interrupt request present interrupt request present Freescale Semiconductor IF5 IF4 IF3 IF2 ...
Page 108
... TIM1 Overflow $FFF1 $FFF2 IF5 TIM1 Channel 1 $FFF3 $FFF4 IF4 TIM1 Channel 0 $FFF5 $FFF6 IF3 PLL $FFF7 $FFF8 IRQ2 IF2 $FFF9 $FFFA IF1 IRQ1 $FFFB $FFFC — SWI $FFFD $FFFE Reset — $FFFF MC68HC908AP A-Family Data Sheet, Rev. 3 Freescale Semiconductor ...
Page 109
... SBSW, in the SIM break status register (SBSR). If the COP disable bit, COPD, in the mask option register is logic 0, then the computer operating properly module (COP) is enabled and remains active in wait mode. Freescale Semiconductor Chapter 21 Break Module (BRK).) The SIM puts the CPU into the break MC68HC908AP A-Family Data Sheet, Rev ...
Page 110
... SSREC bit. 110 WAIT ADDR + 1 SAME PREVIOUS DATA NEXT OPCODE Figure 7-15. Wait Mode Entry Timing $6E0B $6E0C $00FF $A6 $A6 $01 $ CYCLES CYCLES $A6 NOTE MC68HC908AP A-Family Data Sheet, Rev. 3 SAME SAME SAME $00FE $00FD $00FC $6E RST VCT H RST VCT L Freescale Semiconductor ...
Page 111
... SIM Registers The SIM has three memory-mapped registers: • SIM Break Status Register • SIM Reset Status Register • SIM Break Flag Control Register Freescale Semiconductor Figure 7-18 NOTE STOP ADDR + 1 SAME PREVIOUS DATA NEXT OPCODE Figure 7-18. Stop Mode Entry Timing ...
Page 112
... SBSW can be read within the break state SWI routine. The user can modify the return address on the stack by subtracting one from it Wait mode was exited by break interrupt Wait mode was not exited by break interrupt. 112 Reserved MC68HC908AP A-Family Data Sheet, Rev Bit 0 SBSW R R Note 0 Freescale Semiconductor ...
Page 113
... Last reset caused by monitor mode entry when vector locations $FFFE and $FFFF are $FF after POR while IRQ1 = POR or read of SRSR LVI — Low-Voltage Inhibit Reset Bit 1 = Last reset caused by the LVI circuit 0 = POR or read of SRSR Freescale Semiconductor at this time, then the PIN bit may be set, in addition to whatever ...
Page 114
... This read/write bit enables software to clear status bits by accessing status registers while the MCU break state. To clear status bits during the break state, the BCFE bit must be set Status bits clearable during break 0 = Status bits not clearable during break 114 Reserved MC68HC908AP A-Family Data Sheet, Rev Bit Freescale Semiconductor ...
Page 115
... PTA0 and the host computer. PTA0 is used in a wired-OR configuration and requires a pullup resistor security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. Freescale Semiconductor ( reset vector is blank ($FFFE and $FFFF contain TST ...
Page 116
... MC68HC908AP A-Family Data Sheet, Rev. 3 0.1 µ 0.1 µF OSC1 0.01 µ 0.22 µF 1M 6– SW2 (SEE NOTE 1) 8 10k 10k 10k SW1 Freescale Semiconductor RST HC908AP DDA V REFH V REG V REFL SSA CGMXFC OSC1 OSC2 IRQ1 PTA0 PTA1 PTB0 PTA2 ...
Page 117
... Once out of reset, the MCU waits for the host to send eight security bytes. (See security bytes, the MCU sends a break signal (10 consecutive logic 0’s) to the host, indicating that it is ready to receive a command. Freescale Semiconductor NOTE on IRQ1 (condition set 1), then the COP is disabled as long ...
Page 118
Table 8-1. Monitor Mode Signal Requirements and Options Address IRQ1 RST $FFFE/ PTA2 PTA1 PTA0 $FFFF X GND ( TST V TST ...
Page 119
... User Monitor 8.3.2 Data Format Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format. Transmit and receive baud rates must be identical. START BIT 0 BIT 1 BIT Freescale Semiconductor POR RESET NO NORMAL USER IS VECTOR BLANK? YES MONITOR MODE EXECUTE MONITOR ...
Page 120
... IRQ1, then the divide by ratio is set at 1024, regardless of PTB0. DD Table 8-3. Monitor Baud Rate Selection Internal IRQ1 PTB0 Frequency V 0 2.4576 MHz TST V 1 2.4576 MHz TST V X 2.4576 MHz DD MC68HC908AP A-Family Data Sheet, Rev Baud Rate (BPS) 9600 9600 9600 Freescale Semiconductor ...
Page 121
... Table 8-4. READ (Read Memory) Command Description Read byte from memory Operand 2-byte address in high-byte:low-byte order Data Returns contents of specified address Returned Opcode $4A SENT TO MONITOR READ READ ECHO Freescale Semiconductor NOTE ADDRESS ADDRESS ADDRESS ADDRESS HIGH HIGH LOW LOW Figure 8-5. Read Transaction ...
Page 122
... Read next 2 bytes in memory from last address accessed Operand None Data Returns contents of next two addresses Returned Opcode $1A ECHO 122 Command Sequence ADDRESS ADDRESS ADDRESS ADDRESS HIGH HIGH LOW LOW Command Sequence FROM HOST IREAD IREAD DATA MC68HC908AP A-Family Data Sheet, Rev. 3 DATA DATA DATA RETURN Freescale Semiconductor ...
Page 123
... Table 8-8. READSP (Read Stack Pointer) Command Description Reads stack pointer Operand None Data Returns incremented stack pointer value ( Returned high-byte:low-byte order Opcode $0C ECHO Freescale Semiconductor Command Sequence FROM HOST DATA DATA IWRITE IWRITE ECHO Command Sequence FROM HOST SP ...
Page 124
... Command Sequence FROM HOST RUN RUN ECHO HIGH BYTE OF INDEX REGISTER CONDITION CODE REGISTER ACCUMULATOR LOW BYTE OF INDEX REGISTER HIGH BYTE OF PROGRAM COUNTER LOW BYTE OF PROGRAM COUNTER NOTE MC68HC908AP A-Family Data Sheet, Rev Freescale Semiconductor ...
Page 125
... After failing the security sequence, the FLASH module can also be mass erased by executing an erase routine that was downloaded into internal RAM. The mass erase operation clears the security code locations so that all eight security bytes become $FF (blank). Freescale Semiconductor Figure 8-8.) ...
Page 126
... R A $XXXX BUS SPEED (BUS_SPD) DATA SIZE (DATASIZE) START ADDRESS HIGH (ADDRH) START ADDRESS LOW (ADDRL) DATA 0 DATA 1 DATA ARRAY DATA N MC68HC908AP A-Family Data Sheet, Rev. 3 Stack Used Call Address (bytes) $FC34 15 $FCE4 9 $FC00 7 $FF24 17 $FF28 11 M DATA BLOCK Freescale Semiconductor ...
Page 127
... The coding example below is to program 64 bytes of data starting at FLASH location $EE00, with a bus speed of 4.9152 MHz. The coding assumes the data block is already loaded in RAM, with the address pointer, FILE_PTR, pointing to the first byte of the data block. Freescale Semiconductor Table 8-11. PRGRNGE Routine PRGRNGE ...
Page 128
... Data size to be programmed ; FLASH start address ; Reserved data array Table 8-12. ERARNGE Routine ERARNGE Erase a page or the entire array $FCE4 9 bytes Bus speed (BUS_SPD) Data size (DATASIZE) Starting address (ADDRH) Starting address (ADDRL) MC68HC908AP A-Family Data Sheet, Rev. 3 Freescale Semiconductor ...
Page 129
... PRGRNGE (see LDRNGE EQU $FC00 MAIN: BSR INITIALIZATION : : LDHX #FILE_PTR JSR LDRNGE : Freescale Semiconductor 8.5.1 PRGRNGE). Table 8-13. LDRNGE Routine LDRNGE Loads data from a range of locations $FC00 7 bytes Bus speed (BUS_SPD) Data size (DATASIZE) Starting address (ADDRH) Starting address (ADDRL) Data 1 : Data N MC68HC908AP A-Family Data Sheet, Rev ...
Page 130
... Table 8-15. MON_ERARNGE Routine MON_ERARNGE Erase a page or the entire array, in monitor mode $FF28 11 bytes Bus speed Data size Starting address (high byte) Starting address (low byte) ERARNGE), except that MON_ERARNGE returns to the main program MC68HC908AP A-Family Data Sheet, Rev. 3 Freescale Semiconductor ...
Page 131
... Pin Names: References to either timer 1 or timer 2 may be made in the following text by omitting the timer number. For example, TCH0 may refer generically to T1CH0 and T2CH0, and TCH1 may refer to T1CH1 and T2CH1. Freescale Semiconductor Table 9-1. Pin Name Conventions T[1,2]CH0 TIM1 ...
Page 132
... CH0F MS0A MS0B ELS0B ELS0A CH1F MS0A Figure 9-1. TIM Block Diagram NOTE MC68HC908AP A-Family Data Sheet, Rev. 3 TOF INTERRUPT LOGIC TOIE TOV0 PORT CH0MAX T[1,2]CH0 LOGIC INTERRUPT LOGIC CH0IE TOV1 PORT CH1MAX T[1,2]CH1 LOGIC INTERRUPT CH01IE LOGIC CH1IE Freescale Semiconductor ...
Page 133
... Read: High Write: $002C (T2CNTH) Reset: TIM2 Counter Register Read: $002D Low Write: (T2CNTL) Reset: TIM2 Counter Modulo Read: Register High Write: $002E (T2MODH) Reset: Figure 9-2. TIM I/O Register Summary (Sheet Freescale Semiconductor Bit TOF TOIE TSTOP 0 TRST Bit Bit 7 6 ...
Page 134
... Indeterminate after reset Bit Indeterminate after reset CH1F 0 CH1IE MS1A Bit Indeterminate after reset Bit Indeterminate after reset = Unimplemented MC68HC908AP A-Family Data Sheet, Rev ELS0B ELS0A TOV0 ELS1B ELS1A TOV1 Freescale Semiconductor Bit 0 Bit 0 1 CH0MAX 0 Bit 8 Bit 0 CH1MAX 0 Bit 8 Bit 0 9.4.3 ...
Page 135
... PWM pulse is 0. The value in the TIM counter modulo registers and the selected prescaler output determines the frequency of the PWM output. The frequency of an 8-bit PWM signal is variable in 256 increments. Writing Freescale Semiconductor NOTE MC68HC908AP A-Family Data Sheet, Rev. 3 ...
Page 136
... PWM signal generation when changing the PWM pulse width to a new, much larger value. 136 9.9.1 TIM Status and Control OVERFLOW PERIOD OUTPUT OUTPUT COMPARE COMPARE NOTE MC68HC908AP A-Family Data Sheet, Rev. 3 Register. OVERFLOW OUTPUT COMPARE 9.4.4 Pulse Width Freescale Semiconductor ...
Page 137
... Toggling on output compare can also cause incorrect PWM signal generation when changing the PWM pulse width to a new, much larger value the TIM status control register (TSC), clear the TIM stop bit, TSTOP. Freescale Semiconductor NOTE Table 9-3.) NOTE MC68HC908AP A-Family Data Sheet, Rev ...
Page 138
... The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state. (See 138 Registers.) 21.5.4 SIM Break Flag Control MC68HC908AP A-Family Data Sheet, Rev. 3 Register.) Freescale Semiconductor ...
Page 139
... Stops the TIM counter • Resets the TIM counter • Prescales the TIM counter clock Address: T1SC, $0020 and T2SC, $002B Bit 7 Read: TOF Write: 0 Reset: 0 Figure 9-4. TIM Status and Control Register (TSC) Freescale Semiconductor Conventions. NOTE TOIE TSTOP TRST 0 1 ...
Page 140
... Setting the TSTOP and TRST bits simultaneously stops the TIM counter at a value of $0000. PS[2:0] — Prescaler Select Bits These read/write bits select one of the seven prescaler outputs as the input to the TIM counter as Table 9-2 shows. Reset clears the PS[2:0] bits. 140 NOTE NOTE MC68HC908AP A-Family Data Sheet, Rev. 3 Freescale Semiconductor ...
Page 141
... TIM counter resumes counting from $0000 at the next timer clock. Writing to the high byte (TMODH) inhibits the TOF bit and overflow interrupts until the low byte (TMODL) is written. Reset sets the TIM counter modulo registers. Freescale Semiconductor Table 9-2. Prescaler Selection PS0 TIM Clock Source Internal bus clock ÷ ...
Page 142
... Figure 9-10. TIM Channel 1 Status and Control Register (TSC1) CHxF — Channel x Flag Bit 142 NOTE CH0IE MS0B MS0A ELS0B CH1IE MS1A ELS1B MC68HC908AP A-Family Data Sheet, Rev Bit Bit Bit Bit Bit 0 ELS0A TOV0 CH0MAX Bit 0 ELS1A TOV1 CH1MAX Freescale Semiconductor ...
Page 143
... When ELSxB and ELSxA are both clear, channel x is not connected to an I/O port, and pin TCHx is available as a general-purpose I/O pin. the ELSxB and ELSxA bits. Freescale Semiconductor NOTE Table 9-3 shows how ELSxB and ELSxA work. Reset clears MC68HC908AP A-Family Data Sheet, Rev ...
Page 144
... Pin under port control; initial output level low Capture on rising edge only Capture on falling edge only Capture on rising or falling edge Software compare only Toggle output on compare Clear output on compare Set output on compare Toggle output on compare Clear output on compare Set output on compare Freescale Semiconductor ...
Page 145
... Read: Bit 7 Write: Reset: Figure 9-13. TIM Channel 0 Register Low (TCH0L) Address: T1CH1H, $0029 and T2CH1H, $0034 Bit 7 Read: Bit 15 Write: Reset: Figure 9-14. TIM Channel 1 Register High (TCH1H) Freescale Semiconductor OVERFLOW OVERFLOW OUTPUT OUTPUT COMPARE COMPARE Figure 9-11. CHxMAX Latency ...
Page 146
... Timer Interface Module (TIM) Address: T1CH1L, $002A and T2CH1L, $0035 Bit 7 Read: Bit 7 Write: Reset: Figure 9-15. TIM Channel 1 Register Low (TCH1L) 146 Indeterminate after reset MC68HC908AP A-Family Data Sheet, Rev Bit Bit 0 Freescale Semiconductor ...
Page 147
... TACK bit. The first time the TBIF flag is set after enabling the timebase module, the interrupt is generated at approximately half of the overflow period. Subsequent events occur at the exact period. The reference clock OSCCLK is derived from the oscillator module, see Selection. Freescale Semiconductor MC68HC908AP A-Family Data Sheet, Rev. 3 Figure 10-1, starts counting 5 ...
Page 148
... Figure 10-1. Timebase Block Diagram TBR2 TBR1 TBR0 TACK Unimplemented R MC68HC908AP A-Family Data Sheet, Rev. 3 ÷ 2 ÷ 2 ÷ 2 ÷ 2048 TBMINT TBIF SEL Bit 0 TBIE TBON Reserved Freescale Semiconductor TBON TBIE ...
Page 149
... This read/write bit enables the timebase. Timebase may be turned off to reduce power consumption when its function is not necessary. The counter can be initialized by clearing and then setting this bit. Reset clears the TBON bit Timebase enabled 0 = Timebase disabled and the counter initialized to 0’s Freescale Semiconductor NOTE Timebase Interrupt Rate TBR0 Divider ...
Page 150
... In stop mode the timebase register is not accessible by the CPU. If the timebase functions are not required during stop mode, reduce the power consumption by stopping the timebase before enabling the STOP instruction. 150 MC68HC908AP A-Family Data Sheet, Rev. 3 Freescale Semiconductor ...
Page 151
... Noise error – Framing error – Parity error • Receiver framing error detection • Hardware parity checking • 1/16 bit-time noise detection • Configuration register bit, SCIBDSRC, to allow selection of baud rate clock source Freescale Semiconductor NOTE MC68HC908AP A-Family Data Sheet, Rev. 3 151 ...
Page 152
... Figure 11-1. SCI I/O Register Summary MC68HC908AP A-Family Data Sheet, Rev. 3 shows the full names and the generic TxD PTB2/TxD WAKE ILTY PEN ILIE TE RE RWU ORIE NEIE FEIE IDLE BKF Unaffected by reset SCP0 R SCR2 SCR1 Unaffected Freescale Semiconductor Bit 0 PTY 0 SBK 0 PEIE RPF SCR0 0 ...
Page 153
... RE RWU SCRF SBK WAKEUP CONTROL SCIBDSRC FROM CONFIG SL CGMXCLK A ÷ IT12 => => CGMXCLK is from CGM module IT12 = f BUS Freescale Semiconductor INTERNAL BUS TC OR IDLE LOOPS RECEIVE CONTROL CONTROL BKF ENSCI RPF PRE- BAUD SCALER DIVIDER DATA SELECTION ÷ 16 Figure 11-2. SCI Module Block Diagram MC68HC908AP A-Family Data Sheet, Rev ...
Page 154
... Figure 11-3. PARITY NEXT BIT START STOP BIT BIT 7 BIT PARITY NEXT BIT START BIT 7 BIT 8 STOP BIT BIT INTERNAL BUS SCI DATA REGISTER 11-BIT TRANSMIT SHIFT REGISTER TRANSMITTER CONTROL LOGIC SCTE SBK LOOPS SCTIE ENSCI TC TE TCIE Freescale Semiconductor TxD ...
Page 155
... Clears the SCI data register (SCDR) • Clears the R8 bit in SCC3 • Sets the break flag bit (BKF) in SCS2 • May set the overrun (OR), noise flag (NF), parity error (PE), or reception in progress flag (RPF) bits Freescale Semiconductor MC68HC908AP A-Family Data Sheet, Rev. 3 Functional Description 155 ...
Page 156
... After a complete character shifts into the receive shift register, the data portion of the character transfers to the SCDR. The SCI receiver full bit, SCRF, in SCI status register 1 (SCS1) becomes set, indicating that 156 NOTE 1.) MC68HC908AP A-Family Data Sheet, Rev. 3 Freescale Semiconductor ...
Page 157
... SCP0 SL CGMXCLK A PRE- ÷ IT12 SCALER => => BKF RPF M WAKE ILTY PEN PTY Figure 11-5. SCI Receiver Block Diagram Freescale Semiconductor INTERNAL BUS SCR1 SCR2 SCR0 BAUD ÷ 16 DIVIDER DATA H RxD RECOVERY ALL 0s WAKEUP LOGIC PARITY CHECKING IDLE ILIE DMARE SCRF ...
Page 158
... QUALIFICATION VERIFICATION SAMPLING Figure 11-6. Receiver Data Sampling Table 11-2. Start Bit Verification Start Bit Samples Verification 000 Yes 001 Yes 010 Yes 011 No 100 Yes 101 No 110 No 111 No MC68HC908AP A-Family Data Sheet, Rev. 3 LSB DATA Noise Flag Freescale Semiconductor ...
Page 159
... To verify a stop bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. summarizes the results of the stop bit samples. RT8, RT9, and RT10 Freescale Semiconductor Table 11-3. Data Bit Recovery Data Bit Samples ...
Page 160
... DATA SAMPLES Figure 11-7. Slow Data Figure 11-7, the receiver counts 154 RT cycles at the point when 154 147 – × 100 = 4.54% ------------------------- - 154 Figure 11-7, the receiver counts 170 RT cycles at the point when MC68HC908AP A-Family Data Sheet, Rev. 3 STOP Freescale Semiconductor ...
Page 161
... So that the MCU can ignore transmissions intended only for other receivers in multiple-receiver systems, the receiver can be put into a standby state. Setting the receiver wakeup bit, RWU, in SCC2 puts the receiver into a standby state during which receiver interrupts are disabled. Freescale Semiconductor 170 163 – ...
Page 162
... Parity error (PE) — The PE bit in SCS1 is set when the SCI detects a parity error in incoming data. The parity error interrupt enable bit, PEIE, in SCC3 enables PE to generate SCI error CPU interrupt requests. 162 NOTE MC68HC908AP A-Family Data Sheet, Rev. 3 Freescale Semiconductor ...
Page 163
... When the SCI is enabled (ENSCI=1), the PTB2/TxD pin becomes the serial data output, TxD, from the SCI transmitter regardless of the state of the DDRB2 bit in data direction register B (DDRB). The TxD pin is an open-drain output and requires a pullup resistor to be connected for proper SCI operation. Freescale Semiconductor for information on exiting wait mode. for information on exiting stop mode. ...
Page 164
... SCI control register 2 (SCC2) • SCI control register 3 (SCC3) • SCI status register 1 (SCS1) • SCI status register 2 (SCS2) • SCI data register (SCDR) • SCI baud rate register (SCBR) 164 NOTE NOTE MC68HC908AP A-Family Data Sheet, Rev. 3 Freescale Semiconductor ...
Page 165
... M — Mode (Character Length) Bit This read/write bit determines whether SCI characters are eight or nine bits long. (See The ninth bit can serve as an extra stop bit receiver wakeup signal parity bit. Reset clears the M bit 9-bit SCI characters 0 = 8-bit SCI characters Freescale Semiconductor ENSCI ...
Page 166
... Odd 1 8 Even 1 8 Odd MC68HC908AP A-Family Data Sheet, Rev. 3 11-5.) When enabled, the parity function 11-3.) Reset clears the PEN bit. Stop Character Bits Length 1 10 bits 1 11 bits 1 10 bits 1 10 bits 1 11 bits 1 11 bits Freescale Semiconductor ...
Page 167
... ILIE — Idle Line Interrupt Enable Bit This read/write bit enables the IDLE bit to generate SCI receiver CPU interrupt requests. Reset clears the ILIE bit IDLE enabled to generate CPU interrupt requests 0 = IDLE not enabled to generate CPU interrupt requests Freescale Semiconductor TCIE ...
Page 168
... No break characters being transmitted Do not toggle the SBK bit immediately after setting the SCTE bit. Toggling SBK before the preamble begins causes the SCI to send a break character instead of a preamble. 168 NOTE NOTE NOTE MC68HC908AP A-Family Data Sheet, Rev. 3 Freescale Semiconductor ...
Page 169
... SCTE DMA service requests disabled; SCTE CPU interrupt requests enabled ORIE — Receiver Overrun Interrupt Enable Bit This read/write bit enables SCI error CPU interrupt requests generated by the receiver overrun bit, OR SCI error CPU interrupt requests from OR bit enabled 0 = SCI error CPU interrupt requests from OR bit disabled Freescale Semiconductor ...
Page 170
... SCS1 with SCTE set and then writing to SCDR. Reset sets the SCTE bit SCDR data transferred to transmit shift register 0 = SCDR data not transferred to transmit shift register 170 11.8.4 SCI Status Register SCRF IDLE Unimplemented MC68HC908AP A-Family Data Sheet, Rev. 3 1.) Reset clears PEIE Bit Freescale Semiconductor ...
Page 171
... This clearable, read-only bit is set when the SCI detects noise on the RxD pin. NF generates an SCI error CPU interrupt request if the NEIE bit in SCC3 is also set. Clear the NF bit by reading SCS1 and then reading the SCDR. Reset clears the NF bit Noise detected noise detected Freescale Semiconductor MC68HC908AP A-Family Data Sheet, Rev. 3 I/O Registers 171 ...
Page 172
... READ SCDR BYTE 2 DELAYED FLAG CLEARING SEQUENCE BYTE 2 BYTE 3 READ SCS1 SCRF = READ SCDR BYTE 1 Figure 11-13. Flag Clearing Sequence MC68HC908AP A-Family Data Sheet, Rev. 3 BYTE 4 READ SCS1 SCRF = READ SCDR BYTE 3 BYTE 4 READ SCS1 SCRF = READ SCDR BYTE 3 Freescale Semiconductor ...
Page 173
... Reset: R7/T7–R0/T0 — Receive/Transmit Data Bits Reading the SCDR accesses the read-only received data bits, R7–R0. Writing to the SCDR writes the data to be transmitted, T7–T0. Reset has no effect on the SCDR. Do not use read/modify/write instructions on the SCI data register. Freescale Semiconductor ...
Page 174
... Table 11-7. SCI Baud Rate Selection Baud Rate Divisor (BD) 000 001 010 011 100 101 110 111 SCI clock source baud rate = -------------------------------------------- - × × MC68HC908AP A-Family Data Sheet, Rev Bit 0 SCR2 SCR1 SCR0 Reserved Table 11-6. Reset clears SCP1 Table 11-7. Reset clears 128 Freescale Semiconductor ...
Page 175
... Freescale Semiconductor SCR2, SCR1, and SCR0 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 MC68HC908AP A-Family Data Sheet, Rev. 3 ...
Page 176
... Serial Communications Interface Module (SCI) 176 MC68HC908AP A-Family Data Sheet, Rev. 3 Freescale Semiconductor ...
Page 177
... Features of the infrared (IR) sub-module include the following: • IR sub-module enable/disable for infrared SCI or conventional SCI on SCTxD and SCRxD pins • Software selectable infrared modulation/demodulation (3/16, 1/16 or 1/32 width pulses) Freescale Semiconductor NOTE MC68HC908AP A-Family Data Sheet, Rev. 3 177 ...
Page 178
... CKS SCP1 SCP0 Unimplemented R = Reserved MC68HC908AP A-Family Data Sheet, Rev. 3 shows the full names and the generic TxD PTC6/SCTxD WAKE ILTY PEN RWU ORIE NEIE FEIE BKF SCR2 SCR1 TNP1 TNP0 Unaffected Freescale Semiconductor Bit 0 PTY 0 SBK 0 PEIE RPF SCR0 0 IREN 0 ...
Page 179
... When receiving data, the infrared pulses should be detected using an infrared photo diode for conversion to CMOS voltage levels before connecting to the RxD pin for the infrared decoder. The SCI data stream is reconstructed by stretching the "0" pulses. Freescale Semiconductor INTERNAL BUS SCI_TxD SERIAL ...
Page 180
... IR_RxD remains "1". 180 TNP[1:0] TRANSMIT ENCODER IR_RxD RECEIVE DECODER MUX DATA BIT WIDTH DETERMINED BY BAUD RATE Figure 12-4. Infrared SCI Data Example MC68HC908AP A-Family Data Sheet, Rev. 3 IREN IR_TxD SCTxD MUX SCRxD Freescale Semiconductor ...
Page 181
... RE TC RWU SCRF SBK IDLE WAKEUP CONTROL CKS SL A CGMXCLK X B BUS CLOCK => => SCI_R32XCLK SCI_R16XCLK Freescale Semiconductor INTERNAL BUS LOOPS RECEIVE FLAG CONTROL CONTROL BKF ENSCI RPF BAUD RATE GENERATOR DATA SELECTION ÷16 CONTROL Figure 12-5. SCI Module Block Diagram MC68HC908AP A-Family Data Sheet, Rev ...
Page 182
... DATA FORMAT BIT M IN IRSCC1 SET BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 Figure 12-6. SCI Data Formats MC68HC908AP A-Family Data Sheet, Rev. 3 Figure 12-6. PARITY NEXT BIT START STOP BIT BIT 7 BIT PARITY NEXT BIT START BIT 7 BIT 8 STOP BIT BIT Freescale Semiconductor ...
Page 183
... After the preamble shifts out, control logic transfers the IRSCDR data into the transmit shift register. A logic 0 start bit automatically goes into the least significant bit position of the transmit shift register. A logic 1 stop bit goes into the most significant bit position. Freescale Semiconductor BAUD ÷ 16 ...
Page 184
... Toggle the TE bit for a queued idle character when the SCTE bit becomes set and just before writing the next byte to the IRSCDR. 12.5.2.5 Transmitter Interrupts The following conditions can generate CPU interrupt requests from the SCI transmitter: 184 NOTE MC68HC908AP A-Family Data Sheet, Rev. 3 Freescale Semiconductor ...
Page 185
... IRSCDR are empty and that no break or idle character has been generated. The transmission complete interrupt enable bit, TCIE, in IRSCC2 enables the TC bit to generate transmitter CPU interrupt requests. 12.5.3 Receiver Figure 12-8 shows the structure of the SCI receiver. Freescale Semiconductor MC68HC908AP A-Family Data Sheet, Rev. 3 SCI Functional Description 185 ...
Page 186
... WAKEUP LOGIC PARITY CHECKING IDLE ILIE DMARE SCRF SCRIE DMARE SCRF SCRIE DMARE OR ORIE NF NEIE FE FEIE PE PEIE MC68HC908AP A-Family Data Sheet, Rev. 3 SCI DATA REGISTER 11-BIT RECEIVE SHIFT REGISTER SCRF IDLE R8 ILIE SCRIE DMARE OR ORIE NF NEIE FE FEIE PE PEIE Freescale Semiconductor RWU ...
Page 187
... When the falling edge of a possible start bit occurs, the RT clock begins to count to 16. To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and RT7. Table 12-2 summarizes the results of the start bit verification samples. RT3, RT5, and RT7 Freescale Semiconductor START BIT START BIT START BIT QUALIFICATION ...
Page 188
... Determination 000 0 001 0 010 0 011 1 100 0 101 1 110 1 111 1 NOTE Table 12-4. Stop Bit Recovery RT8, RT9, and RT10 Framing Samples Error Flag 000 1 001 1 MC68HC908AP A-Family Data Sheet, Rev. 3 Noise Flag Noise Flag Table 12-4 Noise Flag 0 1 Freescale Semiconductor ...
Page 189
... For an 8-bit character, data sampling of the stop bit takes the receiver 9 bit times × cycles + 10 RT cycles = 154 RT cycles. With the misaligned character shown in the count of the transmitting device is 9 bit times × cycles + 3 RT cycles = 147 RT cycles. Freescale Semiconductor Table 12-4. Stop Bit Recovery RT8, RT9, and RT10 Framing ...
Page 190
... Figure 12-11. Fast Data Figure 12-11, the receiver counts 154 RT cycles at the point when ˙ 154 160 – × 100 = 3.90% ------------------------- - 154 Figure 12-11, the receiver counts 170 RT cycles at the point when MC68HC908AP A-Family Data Sheet, Rev. 3 IDLE OR NEXT CHARACTER Freescale Semiconductor ...
Page 191
... Noise flag (NF) — The NF bit is set when the SCI detects noise on incoming data or break characters, including start, data, and stop bits. The noise error interrupt enable bit, NEIE, in IRSCC3 enables NF to generate SCI error CPU interrupt requests. Freescale Semiconductor 170 176 – ...
Page 192
... I/O Signals The two IRSCI I/O pins are: • PTC6/SCTxD — Transmit data • PTC7/SCRxD — Receive data 192 for information on exiting wait mode. for information on exiting stop mode. MC68HC908AP A-Family Data Sheet, Rev. 3 Freescale Semiconductor ...
Page 193
... X 1. After completion of transmission in progress. 12.9 I/O Registers The following I/O registers control and monitor SCI operation: • IRSCI control register 1 (IRSCC1) • IRSCI control register 2 (IRSCC2) • IRSCI control register 3 (IRSCC3) Freescale Semiconductor NOTE NOTE IRSCC2 TxD Pin [RE] (1) 0 Hi-Z (1) ...
Page 194
... This read/write bit enables the SCI and the SCI baud rate generator. Clearing ENSCI sets the SCTE and TC bits in SCI status register 1 and disables transmitter interrupts. Reset clears the ENSCI bit SCI enabled 0 = SCI disabled 194 ENSCI M WAKE MC68HC908AP A-Family Data Sheet, Rev Bit 0 ILTY PEN PTY Freescale Semiconductor ...
Page 195
... Odd parity 0 = Even parity Changing the PTY bit in the middle of a transmission or reception can generate a parity error. Control Bits M PEN:PTY Freescale Semiconductor Table Figure NOTE Table 12-6. Character Format Selection Character Format Start Data Parity Bits Bits 1 8 None 1 9 None 1 7 ...
Page 196
... TxD returns to the idle condition (logic 1). Clearing and then setting TE during a transmission queues an idle character to be sent after the character currently being transmitted. Reset clears the TE bit Transmitter enabled 0 = Transmitter disabled 196 TCIE SCRIE ILIE MC68HC908AP A-Family Data Sheet, Rev Bit 0 RE RWU SBK Freescale Semiconductor ...
Page 197
... Receiver overrun interrupts – Noise error interrupts – Framing error interrupts – Parity error interrupts Address: $0042 Bit 7 Read: R8 Write: Reset Unimplemented Figure 12-14. IRSCI Control Register 3 (IRSCC3) Freescale Semiconductor NOTE NOTE NOTE DMARE DMATE ORIE Unaffected MC68HC908AP A-Family Data Sheet, Rev. 3 ...
Page 198
... PE. (See PEIE SCI error CPU interrupt requests from PE bit enabled 0 = SCI error CPU interrupt requests from PE bit disabled 198 CAUTION CAUTION 12.9.4 IRSCI Status Register MC68HC908AP A-Family Data Sheet, Rev. 3 1.) Reset clears Freescale Semiconductor ...
Page 199
... This clearable, read-only bit is set when consecutive logic 1s appear on the receiver input. IDLE generates an SCI receiver CPU interrupt request if the ILIE bit in IRSCC2 is also set. Clear the IDLE bit by reading IRSCS1 with IDLE set and then reading the IRSCDR. After the receiver is enabled, Freescale Semiconductor 6 5 ...
Page 200
... READ IRSCDR BYTE 2 DELAYED FLAG CLEARING SEQUENCE BYTE 2 BYTE 3 READ IRSCS1 SCRF = READ IRSCDR BYTE 1 Figure 12-16. Flag Clearing Sequence MC68HC908AP A-Family Data Sheet, Rev. 3 BYTE 4 READ IRSCS1 SCRF = READ IRSCDR BYTE 3 BYTE 4 READ IRSCS1 SCRF = READ IRSCDR BYTE 3 Freescale Semiconductor ...