MC9S08GT60CFD Freescale Semiconductor, MC9S08GT60CFD Datasheet - Page 252

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MC9S08GT60CFD

Manufacturer Part Number
MC9S08GT60CFD
Description
MCU 8BIT 60K FLASH 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet

Specifications of MC9S08GT60CFD

Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Development Support
BDFR — Background Debug Force Reset
15.5.3
The debug module includes nine bytes of register space for three 16-bit registers and three 8-bit control
and status registers. These registers are located in the high register space of the normal memory map so
they are accessible to normal application programs. These registers are rarely if ever accessed by normal
user application programs with the possible exception of a ROM patching mechanism that uses the
breakpoint logic.
15.5.3.1 Debug Comparator A High Register (DBGCAH)
This register contains compare value bits for the high-order eight bits of comparator A. This register is
forced to $00 at reset and can be read at any time or written at any time unless ARM = 1.
15.5.3.2 Debug Comparator A Low Register (DBGCAL)
This register contains compare value bits for the low-order eight bits of comparator A. This register is
forced to $00 at reset and can be read at any time or written at any time unless ARM = 1.
15.5.3.3 Debug Comparator B High Register (DBGCBH)
This register contains compare value bits for the high-order eight bits of comparator B. This register is
forced to $00 at reset and can be read at any time or written at any time unless ARM = 1.
15.5.3.4 Debug Comparator B Low Register (DBGCBL)
This register contains compare value bits for the low-order eight bits of comparator B. This register is
forced to $00 at reset and can be read at any time or written at any time unless ARM = 1.
252
A serial active background mode command such as WRITE_BYTE allows an external debug host to
force a target system reset. Writing 1 to this bit forces an MCU reset. This bit cannot be written from
a user program.
1
BDFR is writable only through serial active background mode debug commands, not from user programs.
DBG Registers and Control Bits
Figure 15-6. System Background Debug Force Reset Register (SBDFR)
Reset:
Read:
Write:
Bit 7
0
0
= Unimplemented or Reserved
MC9S08GB/GT Data Sheet, Rev. 2.3
6
0
0
5
0
0
4
0
1
3
0
0
2
0
0
Freescale Semiconductor
1
0
0
BDFR
Bit 0
0
0
1

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