MC9S08GT60CFD Freescale Semiconductor, MC9S08GT60CFD Datasheet - Page 254

• Manufacturer Part Number: MC9S08GT60CFD
• Description: MCU 8BIT 60K FLASH 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08GT60CFD

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Development Support
15.5.3.7 Debug Control Register (DBGC)
This register can be read or written at any time.
DBGEN — Debug Module Enable
ARM — Arm Control
TAG — Tag/Force Select
BRKEN — Break Enable
RWA — R/W Comparison Value for Comparator A
254
Used to enable the debug module. DBGEN cannot be set to 1 if the MCU is secure.
Controls whether the debugger is comparing and storing information in the FIFO. A write is used to
set this bit (and the ARMF bit) and completion of a debug run automatically clears it. Any debug run
can be manually stopped by writing 0 to ARM or to DBGEN.
Controls whether break requests to the CPU will be tag or force type requests. If BRKEN = 0, this bit
has no meaning or effect.
Controls whether a trigger event will generate a break request to the CPU. Trigger events can cause
information to be stored in the FIFO without generating a break request to the CPU. For an end trace,
CPU break requests are issued to the CPU when the comparator(s) and R/W meet the trigger
requirements. For a begin trace, CPU break requests are issued when the FIFO becomes full. TRGSEL
does not affect the timing of CPU break requests.
When RWAEN = 1, this bit determines whether a read or a write access qualifies comparator A. When
RWAEN = 0, RWA and the R/W signal do not affect comparator A.
1 = DBG enabled.
0 = DBG disabled.
1 = Debugger armed.
0 = Debugger not armed.
1 = CPU breaks requested as tag type requests.
0 = CPU breaks requested as force type requests.
1 = Triggers cause a break request to the CPU.
0 = CPU break requests not enabled.
1 = Comparator A can only match on a read cycle.
0 = Comparator A can only match on a write cycle.
Reset:
Read:
Write:
DBGEN
Bit 7
0
Figure 15-7. Debug Control Register (DBGC)
MC9S08GB/GT Data Sheet, Rev. 2.3
ARM
6
0
TAG
5
0
BRKEN
4
0
RWA
3
0
RWAEN
2
0
Freescale Semiconductor
RWB
1
0
RWBEN
Bit 0
0