MCHC908GR8CFAE Freescale Semiconductor, MCHC908GR8CFAE Datasheet

IC MCU FLSH 8BIT8MHZ 7.5K32-LQFP

MCHC908GR8CFAE

Manufacturer Part Number
MCHC908GR8CFAE
Description
IC MCU FLSH 8BIT8MHZ 7.5K32-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheets

Specifications of MCHC908GR8CFAE

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
21
Program Memory Size
7.5KB (7.5K x 8)
Program Memory Type
FLASH
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 6x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
Controller Family/series
HC08
No. Of I/o's
21
Ram Memory Size
384Byte
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
I2C, SCI, SPI
Rohs Compliant
Yes
Processor Series
HC08G
Core
HC08
Data Bus Width
8 bit
Data Ram Size
384 B
Interface Type
SCI, SPI
Maximum Clock Frequency
8.2 MHz
Number Of Programmable I/os
21
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 6 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

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Freescale Semiconductor, Inc.
MC68HC908GR8
MC68HC908GR4
Technical Data
M68HC08
Microcontrollers
MC68HC908GR8/D
Rev. 4, 6/2002
WWW.MOTOROLA.COM/SEMICONDUCTORS
For More Information On This Product,
Go to: www.freescale.com

Related parts for MCHC908GR8CFAE

MCHC908GR8CFAE Summary of contents

Page 1

... Freescale Semiconductor, Inc. M68HC08 Microcontrollers WWW.MOTOROLA.COM/SEMICONDUCTORS For More Information On This Product, Go to: www.freescale.com MC68HC908GR8 MC68HC908GR4 Technical Data MC68HC908GR8/D Rev. 4, 6/2002 ...

Page 2

... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com ...

Page 3

... Freescale Semiconductor, Inc. MC68HC908GR8 MC68HC908GR4 Technical Data — Rev 4.0 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any ...

Page 4

... Freescale Semiconductor, Inc. Technical Data 4 For More Information On This Product, Go to: www.freescale.com MC68HC908GR8 — Rev 4.0 MOTOROLA ...

Page 5

... Freescale Semiconductor, Inc. Technical Data — MC68HC908GR8 List of Paragraphs Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Section 1. General Description . . . . . . . . . . . . . . . . . . . . 25 Section 2. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Section 3. Low Power Modes Section 4. Resets and Interrupts . . . . . . . . . . . . . . . . . . . 61 Section 5. Analog-to-Digital Converter (ADC Section 6. Break Module (BRK Section 7. Clock Generator Module (CGMC Section 8 ...

Page 6

... Freescale Semiconductor, Inc. List of Paragraphs Section 17. RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 Section 18. Serial Communications Interface (SCI 231 Section 19. System Integration Module (SIM 271 Section 20. Serial Peripheral Interface (SPI 297 Section 21. Timebase Module (TBM 329 Section 22. Timer Interface Module (TIM 335 Section 23. Electrical Specifications 361 Section 24 ...

Page 7

... Freescale Semiconductor, Inc. Technical Data — MC68HC908GR8 1.1 1.2 1.3 1.4 1.5 1.6 2.1 2.2 2.3 2.4 2.5 MC68HC908GR8 — Rev 4.0 MOTOROLA For More Information On This Product, List of Paragraphs Table of Contents List of Tables List of Figures Section 1. General Description Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Features ...

Page 8

... Freescale Semiconductor, Inc. Table of Contents 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 4.1 4.2 4.3 4.4 5.1 5.2 Technical Data 8 For More Information On This Product, Section 3. Low Power Modes Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Analog-to-Digital Converter (ADC Break Module (BRK) ...

Page 9

... Freescale Semiconductor, Inc. 5.3 5.4 5.5 5.6 5.7 5.8 6.1 6.2 6.3 6.4 6.5 6.6 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 MC68HC908GR8 — Rev 4.0 MOTOROLA For More Information On This Product, Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Interrupts Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 I/O Registers ...

Page 10

... Freescale Semiconductor, Inc. Table of Contents 8.1 8.2 8.3 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8 10.9 Technical Data 10 For More Information On This Product, Section 8. Configuration Register (CONFIG) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Functional Description ...

Page 11

... Freescale Semiconductor, Inc. 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 11.9 11.10 STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 12.1 12.2 12.3 12.4 12.5 12.6 12.7 13.1 13.2 13.3 13.4 13.5 MC68HC908GR8 — Rev 4.0 MOTOROLA For More Information On This Product, Section 11. Flash Memory Contents ...

Page 12

... Freescale Semiconductor, Inc. Table of Contents 13.6 13.7 13.8 14.1 14.2 14.3 14.4 14.5 14.6 14.7 15.1 15.2 15.3 15.4 15.5 16.1 16.2 16.3 16.4 16.5 16.6 Technical Data 12 For More Information On This Product, Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180 Keyboard Module During Break Interrupts . . . . . . . . . . . . . . .180 I/O Registers ...

Page 13

... Freescale Semiconductor, Inc. 16.7 17.1 17.2 17.3 Section 18. Serial Communications Interface (SCI) 18.1 18.2 18.3 18.4 18.5 18.6 18.7 18.8 18.9 19.1 19.2 19.3 19.4 19.5 19.6 19.7 19.8 MC68HC908GR8 — Rev 4.0 MOTOROLA For More Information On This Product, Port 225 Section 17 ...

Page 14

... Freescale Semiconductor, Inc. Table of Contents 20.1 20.2 20.3 20.4 20.5 20.6 20.7 20.8 20.9 20.10 Resetting the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 20.11 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .317 20.12 SPI During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .318 20.13 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 20.14 I/O Registers 322 21.1 21.2 21.3 21.4 21 ...

Page 15

... Freescale Semiconductor, Inc. 22.2 22.3 22.4 22.5 22.6 22.7 22.8 22.9 22.10 I/O Registers 349 23.1 23.2 23.3 23.4 23.5 23.6 23.7 23.8 23.9 23.10 Output Low-Voltage Characteristics . . . . . . . . . . . . . . . . . . . . 373 23.11 Typical Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 23.12 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 23.13 5.0 V SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379 23 ...

Page 16

... Freescale Semiconductor, Inc. Table of Contents 23.16 Clock Generation Module Characteristics . . . . . . . . . . . . . . . 383 23.17 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385 24.1 24.2 24.3 24.4 24.5 25.1 25.2 25.3 25.4 Technical Data 16 For More Information On This Product, Section 24. Mechanical Specifications Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387 32-Pin LQFP (Case #873A .388 28-Pin PDIP (Case #710) ...

Page 17

... Freescale Semiconductor, Inc. Technical Data — MC68HC908GR8 Table 2-1 4-1 4-2 5-1 5-2 7-1 7-2 7-3 10-1 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 10-2 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 11-1 Examples of protect start address 166 14-1 LVIOUT Bit Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 15-1 Monitor Mode Signal Requirements and Options . . . . . . . . . . 193 15-2 Mode Differences ...

Page 18

... Freescale Semiconductor, Inc. List of Tables 18-3 Data Bit Recovery 244 18-4 Stop Bit Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 18-5 Character Format Selection . . . . . . . . . . . . . . . . . . . . . . . . . .255 18-6 SCI Baud Rate Prescaling . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 18-7 SCI Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 18-8 SCI Baud Rate Selection Examples . . . . . . . . . . . . . . . . . . . . 268 19-1 Signal Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 19-2 PIN Bit Set Timing ...

Page 19

... Freescale Semiconductor, Inc. Technical Data — MC68HC908GR8 Figure 1-1 1-2 1-3 1-4 2-1 2-2 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 5-1 5-2 5-3 5-4 6-1 6-2 6-3 6-4 6-5 6-6 6-7 7-1 7-2 7-3 MC68HC908GR8 — Rev 4.0 ...

Page 20

... Freescale Semiconductor, Inc. List of Figures 7-4 7-5 7-6 7-7 7-8 7-9 7-10 PLL Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 8-1 8-2 9-1 9-2 10-1 CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 10-2 Accumulator ( 141 10-3 Index register (H:X 141 10-4 Stack pointer (SP 142 10-5 Program counter (PC 143 10-6 Condition code register (CCR 143 11-1 FLASH Control Register (FLCR) ...

Page 21

... Freescale Semiconductor, Inc. 15-8 Monitor Mode Entry Timing 203 16-1 I/O Port Register Summary 206 16-2 Port A Data Register (PTA .209 16-3 Data Direction Register A (DDRA 210 16-4 Port A I/O Circuit 211 16-5 Port A Input Pullup Enable Register (PTAPUE 212 16-6 Port B Data Register (PTB .213 16-7 Data Direction Register B (DDRB) ...

Page 22

... Freescale Semiconductor, Inc. List of Figures 19-3 CGM Clock Signals 275 19-4 External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 19-5 Internal Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 19-6 Sources of Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 19-7 POR Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 19-8 Interrupt Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 19-9 Interrupt Recovery Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 19-10 Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 19-11 Interrupt Recognition Example ...

Page 23

... Freescale Semiconductor, Inc. 22-2 TIM I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 22-3 PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . 343 22-4 TIM Status and Control Register (TSC 349 22-5 TIM Counter Registers High (TCNTH 352 22-6 TIM Counter Registers Low (TCNTL 352 22-7 TIM Counter Modulo Register High (TMODH .353 22-8 TIM Counter Modulo Register Low (TMODL) ...

Page 24

... Freescale Semiconductor, Inc. List of Figures 23-12 Typical Low-Side Driver Characteristics – Ports PTB5–PTB0, 23-13 Typical Operating IDD, with All Modules Turned On 23-14 Typical Wait Mode IDD, with all Modules Disabled 23-15 Typical Stop Mode IDD, with all Modules Disabled 23-16 SPI Master Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .381 23-17 SPI Slave Timing ...

Page 25

... Freescale Semiconductor, Inc. Technical Data — MC68HC908GR8 1.1 Contents 1.2 1.3 1.4 1.5 1.6 1.2 Introduction The MC68HC908GR8 is a member of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types ...

Page 26

... Freescale Semiconductor, Inc. General Description 1.3 Features For convenience, features have been organized to reflect: • • 1.3.1 Standard Features of the MC68HC908GR8 • • • • • • • • • • security feature is absolutely secure. However, Motorola’s strategy is to make reading or copying the FLASH difficult for unauthorized users ...

Page 27

... Freescale Semiconductor, Inc. • • • • • • • • • • • • • • • MC68HC908GR8 — Rev 4.0 MOTOROLA For More Information On This Product, 7680 bytes of on-chip FLASH memory on the MC68HC908GR8 and 4096 bytes of on-chip FLASH memory on the ...

Page 28

... Freescale Semiconductor, Inc. General Description • • • 1.3.2 Features of the CPU08 Features of the CPU08 include: • • • • • • • • • • 1.4 MCU Block Diagram Figure 1-1 Technical Data 28 For More Information On This Product, 4-bit keyboard wakeup port ...

Page 29

... Freescale Semiconductor, Inc. PORTA PORTB PORTC DDRA DDRB DDRC MC68HC908GR8 — Rev 4.0 MOTOROLA For More Information On This Product, PORTD PORTE DDRD DDRE Figure 1-1. MCU Block Diagram General Description Go to: www.freescale.com General Description MCU Block Diagram Technical Data 29 ...

Page 30

... Freescale Semiconductor, Inc. General Description 1.5 Pin Assignments NOTE: Ports PTB4, PTB5, PTC0, and PTC1 are available only with the QFP. Technical Data 30 For More Information On This Product, RST 1 PTE0/TxD 2 PTE1/RxD 3 IRQ 4 PTD0/SS 5 PTD1/MISO 6 PTD2/MOSI 7 PTD3/SPSCK 8 Figure 1-2. QFP Pin Assignments General Description Go to: www ...

Page 31

... Freescale Semiconductor, Inc. NOTE: Ports PTB4, PTB5, PTC0, and PTC1 are available only with the QFP. 1.6 Pin Functions Descriptions of the pin functions are provided here. 1.6.1 Power Supply Pins (V V and V DD from a single power supply. Fast signal transitions on MCU pins place high, short-duration current demands on the power supply ...

Page 32

... Freescale Semiconductor, Inc. General Description 1.6.2 Oscillator Pins (OSC1 and OSC2) The OSC1 and OSC2 pins are the connections for the on-chip oscillator circuit. See 1.6.3 External Reset Pin (RST) A logic 0 on the RST pin forces the MCU to a known startup state. RST is bidirectional, allowing a reset of the entire system ...

Page 33

... Freescale Semiconductor, Inc. 1.6.6 External Filter Capacitor Pin (CGMXFC) CGMXFC is an external filter capacitor connection for the CGM. See Clock Generator Module 1.6.7 Analog Power Supply/Reference Pins (V V DDAD converter. Decoupling of these pins should be as per the digital supply. NOTE: V REFH ...

Page 34

... Freescale Semiconductor, Inc. General Description 1.6.10 Port C I/O Pins (PTC1–PTC0) PTC1–PTC0 are general-purpose, bidirectional I/O port pins. See Input/Output Ports QFP packages. These port pins also have selectable pullups when configured for input mode. The pullups are disengaged when configured for output mode. ...

Page 35

... Freescale Semiconductor, Inc. Technical Data — MC68HC908GR8 2.1 Contents 2.2 2.3 2.4 2.5 2.2 Introduction The CPU08 can address 64K bytes of memory space. The memory map, shown in • • • • • 2.3 Unimplemented Memory Locations Accessing an unimplemented location can cause an illegal address reset if illegal address resets are enabled ...

Page 36

... Freescale Semiconductor, Inc. Memory Map 2.4 Reserved Memory Locations Accessing a reserved location can have unpredictable effects on MCU operation. In the reserved locations are marked with the word Reserved or with the letter R. 2.5 Input/Output (I/O) Section Most of the control, status, and data registers are in the zero page area of $0000– ...

Page 37

... Freescale Semiconductor, Inc. $0000 $003F $0040 $01BF $01C0 $1BFF $1C00 $1E1F $1E20 $DFFF $E000 $EDFF $EE00 $FDFF $FE00 $FE01 $FE02 $FE03 $FE09 $FE0A $FE0B $FE07 MC68HC908GR8 — Rev 4.0 MOTOROLA For More Information On This Product, I/O Registers 64 Bytes RAM 384 Bytes ...

Page 38

... Freescale Semiconductor, Inc. Memory Map $FE08 $FE09 $FE0A $FE0B $FE0C $FE0D $FE0F $FE10 $FE1F $FE20 $FF55 $FF56 $FF7D $FF7E $FF7F $FFDB $FFDC Note: $FFF6–$FFFD contains 8 security bytes $FFFE $FFFF Figure 2-1. Memory Map (Continued) Technical Data 38 For More Information On This Product, ...

Page 39

... Freescale Semiconductor, Inc. Addr. Register Name Read: Port A Data Register $0000 Write: (PTA) Reset: Read: Port B Data Register $0001 Write: (PTB) Reset: Read: Port C Data Register $0002 Write: (PTC) Reset: Read: Port D Data Register $0003 Write: (PTD) Reset: Read: Data Direction Register A ...

Page 40

... Freescale Semiconductor, Inc. Memory Map Addr. Register Name Read: $000A Unimplemented Write: Reset: Read: $000B Unimplemented Write: Reset: Read: Data Direction Register E $000C Write: (DDRE) Reset: Read: Port A Input Pullup Enable $000D Write: Register (PTAPUE) Reset: Read: Port C Input Pullup Enable ...

Page 41

... Freescale Semiconductor, Inc. Addr. Register Name Read: SCI Control Register 2 $0014 Write: (SCC2) Reset: Read: SCI Control Register 3 $0015 Write: (SCC3) Reset: Read: SCI Status Register 1 $0016 Write: (SCS1) Reset: Read: SCI Status Register 2 $0017 Write: (SCS2) Reset: Read: SCI Data Register ...

Page 42

... Freescale Semiconductor, Inc. Memory Map Addr. Register Name Read: Configuration Register 2 $001E (CONFIG2)† Write: Reset: Read: Configuration Register 1 $001F Write: † (CONFIG1) Reset: Read: Timer 1 Status and Control $0020 Write: Register (T1SC) Reset: Read: Timer 1 Counter Register $0021 Write: High (T1CNTH) ...

Page 43

... Freescale Semiconductor, Inc. Addr. Register Name Read: Timer 1 Channel 1 Status $0028 and Control Register Write: (T1SC1) Reset: Read: Timer 1 Channel 1 $0029 Write: Register High (T1CH1H) Reset: Read: Timer 1 Channel 1 $002A Write: Register Low (T1CH1L) Reset: Read: Timer 2 Status and Control $002B ...

Page 44

... Freescale Semiconductor, Inc. Memory Map Addr. Register Name Read: Timer 2 Channel 0 $0032 Write: Register Low (T2CH0L) Reset: Read: Unimplemented $0033 Write: Reset: Read: $0034 Unimplemented Write: Reset: Read: $0035 Unimplemented Write: Reset: Read: PLL Control Register $0036 Write: (PCTL) Reset: Read: ...

Page 45

... Freescale Semiconductor, Inc. Addr. Register Name Read: Analog-to-Digital Status $003C and Control Register Write: (ADSCR) Reset: Read: Analog-to-Digital Data $003D Write: Register (ADR) Reset: Read: Analog-to-Digital Input $003E Write: Clock Register (ADCLK) Reset: Read: $003F Unimplemented Write: Reset: Read: SIM Break Status Register ...

Page 46

... Freescale Semiconductor, Inc. Memory Map Addr. Register Name Read: Interrupt Status Register 3 $FE0B Write: (INT3) Reset: Read: FLASH Test Control $FE07 Write: Register (FLTCR) Reset: Read: FLASH Control Register $FE08 Write: (FLCR) Reset: Read: Break Address Register $FE09 Write: High (BRKH) ...

Page 47

... Freescale Semiconductor, Inc. Vector Priority MC68HC908GR8 — Rev 4.0 MOTOROLA For More Information On This Product, Table 2-1. Vector Addresses Vector Address Lowest $FFDC IF16 $FFDD $FFDE IF15 $FFDF $FFE0 IF14 $FFE1 $FFE2 IF13 $FFE3 $FFE4 IF12 $FFE5 $FFE6 IF11 $FFE7 $FFE8 ...

Page 48

... Freescale Semiconductor, Inc. Memory Map Technical Data 48 For More Information On This Product, Memory Map Go to: www.freescale.com MC68HC908GR8 — Rev 4.0 MOTOROLA ...

Page 49

... Freescale Semiconductor, Inc. Technical Data — MC68HC908GR8 3.1 Contents 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.2 Introduction The MCU may enter two low-power modes: wait mode and stop mode. They are common to all HC08 MCUs and are entered through instruction execution ...

Page 50

... Freescale Semiconductor, Inc. Low Power Modes 3.2.1 Wait Mode The WAIT instruction puts the MCU in a low-power standby mode in which the CPU clock is disabled but the bus clock continues to run. Power consumption can be further reduced by disabling the LVI module and/or the timebase module through bits in the CONFIG register. (See Configuration Register 3 ...

Page 51

... Freescale Semiconductor, Inc. 3.4 Break Module (BRK) 3.4.1 Wait Mode If enabled, the break module is active in wait mode. In the break routine, the user can subtract one from the return address on the stack if the BW bit in the break status register is set. 3.4.2 Stop Mode The break module is inactive in stop mode ...

Page 52

... Freescale Semiconductor, Inc. Low Power Modes 3.6 Clock Generator Module (CGM) 3.6.1 Wait Mode The CGM remains active in wait mode. Before entering wait mode, software can disengage and turn off the PLL by clearing the BCS and PLLON bits in the PLL control register (PCTL). Less power-sensitive applications can disengage the PLL without turning it off ...

Page 53

... Freescale Semiconductor, Inc. 3.7.2 Stop Mode Stop mode turns off the CGMXCLK input to the COP and clears the COP prescaler. Service the COP immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering or exiting stop mode. The STOP bit in the configuration register (CONFIG) enables the STOP instruction ...

Page 54

... Freescale Semiconductor, Inc. Low Power Modes 3.9.2 Stop Mode The keyboard module remains active in stop mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of stop mode. 3.10 Low-Voltage Inhibit Module (LVI) 3 ...

Page 55

... Freescale Semiconductor, Inc. 3.11.2 Stop Mode The SCI module is inactive in stop mode. The STOP instruction does not affect SCI register states. SCI module operation resumes after the MCU exits stop mode. Because the internal clock is inactive during stop mode, entering stop mode during an SCI transmission or reception results in invalid data ...

Page 56

... Freescale Semiconductor, Inc. Low Power Modes 3.13.2 Stop Mode The TIM is inactive in stop mode. The STOP instruction does not affect register states or the state of the TIM counter. TIM operation resumes when the MCU exits stop mode after an external interrupt. 3.14 Timebase Module (TBM) 3 ...

Page 57

... Freescale Semiconductor, Inc. 3.15 Exiting Wait Mode These events restart the CPU clock and load the program counter with the reset vector or with an interrupt vector: • • • • • • • • • MC68HC908GR8 — Rev 4.0 MOTOROLA For More Information On This Product, External reset — ...

Page 58

... Freescale Semiconductor, Inc. Low Power Modes • • • • 3.16 Exiting Stop Mode These events restart the system clocks and load the program counter with the reset vector or with an interrupt vector: • • Technical Data 58 For More Information On This Product, – ...

Page 59

... Freescale Semiconductor, Inc. Low Power Modes • • • Upon exit from stop mode, the system clocks begin running after an oscillator stabilization delay. A 12-bit stop recovery counter inhibits the system clocks for 4096 CGMXCLK cycles after the reset or external interrupt. The short stop recovery bit, SSREC, in the configuration register controls the oscillator stabilization delay during stop recovery ...

Page 60

... Freescale Semiconductor, Inc. Low Power Modes Technical Data 60 For More Information On This Product, Low Power Modes Go to: www.freescale.com MC68HC908GR8 — Rev 4.0 MOTOROLA ...

Page 61

... Freescale Semiconductor, Inc. Technical Data — MC68HC908GR8 4.1 Contents 4.2 4.3 4.4 4.2 Introduction Resets and interrupts are responses to exceptional events during program execution. A reset re-initializes the MCU to its startup condition. An interrupt vectors the program counter to a service routine. 4.3 Resets A reset immediately returns the MCU to a known startup condition and begins program execution from a user-defined memory location ...

Page 62

... Freescale Semiconductor, Inc. Resets and Interrupts 4.3.2 External Reset A logic 0 applied to the RST pin for a time, t reset. An external reset sets the PIN bit in the SIM reset status register. 4.3.3 Internal Reset Sources: • • • • • All internal reset sources pull the RST pin low for 32 CGMXCLK cycles to allow resetting of external devices ...

Page 63

... Freescale Semiconductor, Inc. A power-on reset: • • • • • OSC1 (1) PORRST CGMXCLK CGMOUT RST PIN INTERNAL RESET 1. PORRST is an internally generated power-on reset pulse. Figure 4-2. Power-On Reset Recovery 4.3.3.2 COP Reset A COP reset is an internal reset caused by an overflow of the COP counter ...

Page 64

... Freescale Semiconductor, Inc. Resets and Interrupts 4.3.3.3 Low-Voltage Inhibit Reset A low-voltage inhibit (LVI) reset is an internal reset caused by a drop in the power supply voltage to the LVI trip voltage LVI reset: • • • • • 4.3.3.4 Illegal Opcode Reset An illegal opcode reset is an internal reset caused by an opcode that is not in the instruction set ...

Page 65

... Freescale Semiconductor, Inc. 4.3.4 SIM Reset Status Register This read-only register contains flags to show reset sources. All flag bits are automatically cleared following a read of the register. Reset service can read the SIM reset status register to clear the register after power- on reset and to determine the source of any subsequent reset. ...

Page 66

... Freescale Semiconductor, Inc. Resets and Interrupts ILOP — Illegal Opcode Reset Bit 1 = Last reset caused by an illegal opcode 0 = POR or read of SRSR ILAD — Illegal Address Reset Bit 1 = Last reset caused by an opcode fetch from an illegal address 0 = POR or read of SRSR LVI — Low-Voltage Inhibit Reset Bit ...

Page 67

... Freescale Semiconductor, Inc. STACKING ORDER After every instruction, the CPU checks all pending interrupts if the I bit is not set. If more than one interrupt is pending when an instruction is done, the highest priority interrupt is serviced first. In the example shown in Figure service routine, the pending interrupt is serviced before the LDA instruction is executed. MC68HC908GR8 — ...

Page 68

... Freescale Semiconductor, Inc. Resets and Interrupts The LDA opcode is prefetched by both the INT1 and INT2 RTI instructions. However, in the case of the INT1 RTI prefetch, this is a redundant operation. NOTE: To maintain compatibility with the M6805 Family, the H register is not pushed on the stack during interrupt entry. If the interrupt service routine modifies the H register or uses the indexed addressing mode, save the H register and then restore it prior to exiting the routine ...

Page 69

... Freescale Semiconductor, Inc. YES MC68HC908GR8 — Rev 4.0 MOTOROLA For More Information On This Product, FROM RESET YES BREAK INTERRUPT ? NO I BIT SET? I BIT SET? NO YES IRQ INTERRUPT ? NO YES CGM INTERRUPT ? NO OTHER YES INTERRUPTS ? NO STACK CPU REGISTERS LOAD PC WITH INTERRUPT VECTOR FETCH NEXT ...

Page 70

... Freescale Semiconductor, Inc. Resets and Interrupts 4.4.2 Sources The sources in Source Reset SWI instruction IRQ pin CGM (PLL) TIM1 channel 0 TIM1 channel 1 TIM1 overflow TIM2 channel 0 TIM2 overflow SPI receiver full SPI overflow SPI mode fault SPI transmitter empty SCI receiver overrun ...

Page 71

... Freescale Semiconductor, Inc. 4.4.2.1 SWI Instruction The software interrupt instruction (SWI) causes a non-maskable interrupt. NOTE: A software interrupt pushes PC onto the stack. An SWI does not push PC – hardware interrupt does. 4.4.2.2 Break Interrupt The break module causes the CPU to execute an SWI instruction at a software-programmable break point ...

Page 72

... Freescale Semiconductor, Inc. Resets and Interrupts 4.4.2.6 TIM2 TIM2 CPU interrupt sources: • • 4.4.2.7 SPI SPI CPU interrupt sources: • • • Technical Data 72 For More Information On This Product, TIM2 overflow flag (TOF) — The TOF bit is set when the TIM2 counter value rolls over to $0000 after matching the value in the TIM2 counter modulo registers ...

Page 73

... Freescale Semiconductor, Inc. • 4.4.2.8 SCI SCI CPU interrupt sources: • • • • • MC68HC908GR8 — Rev 4.0 MOTOROLA For More Information On This Product, Overflow bit (OVRF) — The OVRF bit is set if software does not read the byte in the receive data register before the next full byte enters the shift register ...

Page 74

... Freescale Semiconductor, Inc. Resets and Interrupts • • • 4.4.2.9 KBD0–KBD4 Pins A logic keyboard interrupt pin latches an external interrupt request. 4.4.2.10 ADC (Analog-to-Digital Converter) When the AIEN bit is set, the ADC module is capable of generating a CPU interrupt after each ADC conversion. The COCO/IDMAS bit is not used as a conversion complete flag when interrupts are enabled ...

Page 75

... Freescale Semiconductor, Inc. 4.4.3 Interrupt Status Registers The flags in the interrupt status registers identify maskable interrupt sources. status register flags that they set. The interrupt status registers can be useful for debugging. Reset SWI instruction IRQ pin CGM (PLL) TIM1 channel 0 TIM1 channel 1 ...

Page 76

... Freescale Semiconductor, Inc. Resets and Interrupts 4.4.3.1 Interrupt Status Register 1 Address: Read: Write: Reset: IF6–IF1 — Interrupt Flags 6–1 These flags indicate the presence of interrupt requests from the sources shown Interrupt request present interrupt request present Bit 1 and Bit 0 — Always read 0 4 ...

Page 77

... Freescale Semiconductor, Inc. 4.4.3.3 Interrupt Status Register 3 Address: Read: Write: Reset: IF16–IF15 — Interrupt Flags 16–15 This flag indicates the presence of an interrupt request from the source shown Interrupt request present interrupt request present Bits 7–2 — Always read 0 MC68HC908GR8 — Rev 4.0 ...

Page 78

... Freescale Semiconductor, Inc. Resets and Interrupts Technical Data 78 For More Information On This Product, Resets and Interrupts Go to: www.freescale.com MC68HC908GR8 — Rev 4.0 MOTOROLA ...

Page 79

... Freescale Semiconductor, Inc. Technical Data — MC68HC908GR8 Section 5. Analog-to-Digital Converter (ADC) 5.1 Contents 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.2 Introduction This section describes the 8-bit analog-to-digital converter (ADC). For further information regarding analog-to-digital converters on Motorola microcontrollers, please consult the HC08 ADC Reference Manual, ADCRM/AD. MC68HC908GR8 — ...

Page 80

... Freescale Semiconductor, Inc. Analog-to-Digital Converter (ADC) 5.3 Features Features of the ADC module include: • • • • • • 5.4 Functional Description The ADC provides six pins for sampling external sources at pins PTB5/ATD5–PTB0/ATD0. An analog multiplexer allows the single ADC converter to select one of six ADC channels as ADC voltage in (V ...

Page 81

... Freescale Semiconductor, Inc. INTERNAL DATA BUS INTERRUPT LOGIC AIEN 5.4.1 ADC Port I/O Pins PTB5/ATD5–PTB0/ATD0 are general-purpose I/O (input/output) pins that share with the ADC channels. The channel select bits define which ADC channel/port pin will be used as the input signal. The ADC overrides the port I/O logic by forcing that pin as input to the ADC ...

Page 82

... Freescale Semiconductor, Inc. Analog-to-Digital Converter (ADC) 5.4.2 Voltage Conversion When the input voltage to the ADC equals V signal to $FF (full scale). If the input voltage equals V converts it to $00. Input voltages between V straight-line linear conversion. All other input voltages will result in $FF, if greater than V ...

Page 83

... Freescale Semiconductor, Inc. 5.4.5 Accuracy and Precision The conversion process is monotonic and has no missing codes. 5.5 Interrupts When the AIEN bit is set, the ADC module is capable of generating CPU interrupts after each ADC conversion. A CPU interrupt is generated if the COCO/IDMAS bit is at logic 0. If COCO/IDMAS bit is set, a DMA interrupt is generated ...

Page 84

... Freescale Semiconductor, Inc. Analog-to-Digital Converter (ADC) 5.7.1 ADC Analog Power Pin (V The ADC analog portion uses V V DDAD necessary to ensure clean V NOTE: For maximum noise immunity, route V capacitors as close as possible to the package. 5.7.2 ADC Analog Ground Pin (V The ADC analog portion uses V ...

Page 85

... Freescale Semiconductor, Inc. 5.8 I/O Registers These I/O registers control and monitor ADC operation: • • • 5.8.1 ADC Status and Control Register Function of the ADC status and control register (ADSCR) is described here. Address: $0003C Read: Write: Reset: COCO/IDMAS — Conversions Complete/Interrupt DMA Select Bit ...

Page 86

... Freescale Semiconductor, Inc. Analog-to-Digital Converter (ADC) AIEN — ADC Interrupt Enable Bit When this bit is set, an interrupt is generated at the end of an ADC conversion. The interrupt signal is cleared when the data register is read or the status/control register is written. Reset clears the AIEN bit. ...

Page 87

... Freescale Semiconductor, Inc. ADCH4 NOTE unknown channel is selected it should be made clear what value the user will read from the ADC Data Register, unknown or reserved is not specific enough. 5.8.2 ADC Data Register One 8-bit result register, ADC data register (ADR), is provided. This register is updated each time an ADC conversion completes ...

Page 88

... Freescale Semiconductor, Inc. Analog-to-Digital Converter (ADC) 5.8.3 ADC Clock Register The ADC clock register (ADCLK) selects the clock frequency for the ADC. Address: $0003E Read: Write: Reset: ADIV2–ADIV0 — ADC Clock Prescaler Bits ADIV2–ADIV0 form a 3-bit field which selects the divide ratio used by the ADC to generate the internal ADC clock ...

Page 89

... Freescale Semiconductor, Inc. If the external clock (CGMXCLK) is equal to or greater than 1 MHz, CGMXCLK can be used as the clock source for the ADC. If CGMXCLK is less than 1 MHz, use the PLL-generated bus clock as the clock source. As long as the internal ADC clock is at approximately 1 MHz, correct operation can be guaranteed. ...

Page 90

... Freescale Semiconductor, Inc. Analog-to-Digital Converter (ADC) Technical Data 90 For More Information On This Product, Analog-to-Digital Converter (ADC) Go to: www.freescale.com MC68HC908GR8 — Rev 4.0 MOTOROLA ...

Page 91

... Freescale Semiconductor, Inc. Technical Data — MC68HC908GR8 6.1 Contents 6.2 6.3 6.4 6.5 6.6 6.2 Introduction This section describes the break module. The break module can generate a break interrupt that stops normal program flow at a defined address to enter a background program. 6.3 Features Features of the break module include: • ...

Page 92

... Freescale Semiconductor, Inc. Break Module (BRK) 6.4 Functional Description When the internal address bus matches the value written in the break address registers, the break module issues a breakpoint signal to the CPU. The CPU then loads the instruction register with a software interrupt instruction (SWI) after completion of the current CPU instruction ...

Page 93

... Freescale Semiconductor, Inc. Addr. Register Name Read: SIM Break Status Register $FE00 Write: (SBSR) Reset: Read: SIM Break Flag Control $FE03 Write: Register (SBFCR) Reset: Read: Break Address Register $FE09 Write: High (BRKH) Reset: Read: Break Address Register $FE0A Write: Low (BRKL) ...

Page 94

... Freescale Semiconductor, Inc. Break Module (BRK) The break interrupt begins after completion of the CPU instruction in progress. If the break address register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately. 6.4.3 TIMI and TIM2 During Break Interrupts A break interrupt stops the timer counters. ...

Page 95

... Freescale Semiconductor, Inc. • • • 6.6.1 Break Status and Control Register The break status and control register (BRKSCR) contains break module enable and status bits. Address: Read: Write: Reset: Figure 6-3. Break Status and Control Register (BRKSCR) BRKE — Break Enable Bit This read/write bit enables breaks on break address register matches ...

Page 96

... Freescale Semiconductor, Inc. Break Module (BRK) 6.6.2 Break Address Registers The break address registers (BRKH and BRKL) contain the high and low bytes of the desired breakpoint address. Reset clears the break address registers. Address: Read: Write: Reset: Address: Read: Write: Reset: 6 ...

Page 97

... Freescale Semiconductor, Inc. BW — Break Wait Bit This read/write bit is set when a break interrupt causes an exit from wait mode. Clear BW by writing a logic 0 to it. Reset clears BW Break interrupt during wait mode break interrupt during wait mode BW can be read within the break interrupt routine. The user can modify the return address on the stack by subtracting 1 from it ...

Page 98

... Freescale Semiconductor, Inc. Break Module (BRK) 6.6.4 Break Flag Control Register The break flag control register (SBFCR) contains a bit that enables software to clear status bits while the MCU break state. Address: Read: Write: Reset: BCFE — Break Clear Flag Enable Bit This read/write bit enables software to clear status bits by accessing status registers while the MCU break state ...

Page 99

... Freescale Semiconductor, Inc. Technical Data — MC68HC908GR8 Section 7. Clock Generator Module (CGMC) 7.1 Contents 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.2 Introduction This section describes the clock generator module. The CGMC generates the crystal clock signal, CGMXCLK, which operates at the frequency of the crystal ...

Page 100

... Freescale Semiconductor, Inc. Clock Generator Module (CGMC) 7.3 Features Features of the CGMC include: • • • • • • • • 7.4 Functional Description The CGMC consists of three major submodules: • • • Figure 7-1 Technical Data 100 For More Information On This Product, ...

Page 101

... Freescale Semiconductor, Inc. OSCILLATOR (OSC) OSC2 OSC1 SIMOSCEN (FROM SIM) OSCSTOPENB (FROM CONFIG) PHASE-LOCKED LOOP (PLL) CGMRDV REFERENCE DIVIDER RDS3–RDS0 V DDA PHASE DETECTOR LOCK DETECTOR LOCK MUL11–MUL0 CGMVDV FREQUENCY DIVIDER MC68HC908GR8 — Rev 4.0 MOTOROLA For More Information On This Product, ...

Page 102

... Freescale Semiconductor, Inc. Clock Generator Module (CGMC) 7.4.1 Crystal Oscillator Circuit The crystal oscillator circuit consists of an inverting amplifier and an external crystal. The OSC1 pin is the input to the amplifier and the OSC2 pin is the output. The SIMOSCEN signal from the system integration module (SIM) or the OSCSTOPENB bit in the CONFIG register enable the crystal oscillator circuit ...

Page 103

... Freescale Semiconductor, Inc. The operating range of the VCO is programmable for a wide range of frequencies and for maximum immunity to external noise, including supply and CGM/XFC noise. The VCO frequency is bound to a range from roughly one-half to twice the center-of-range frequency, f Modulating the voltage on the CGM/XFC pin changes the frequency within this range ...

Page 104

... Freescale Semiconductor, Inc. Clock Generator Module (CGMC) frequency, f condition based on this comparison. 7.4.4 Acquisition and Tracking Modes The PLL filter is manually or automatically configurable into one of two operating modes: • • 7.4.5 Manual and Automatic PLL Bandwidth Modes The PLL can change the bandwidth or operational mode of the loop filter manually or automatically ...

Page 105

... Freescale Semiconductor, Inc. to use as the source for the base clock. (See Circuit.) If the VCO is selected as the source for the base clock and the LOCK bit is clear, the PLL has suffered a severe noise hit and the software must take appropriate action, depending on the application. ...

Page 106

... Freescale Semiconductor, Inc. Clock Generator Module (CGMC) • • • 7.4.6 Programming the PLL The following procedure shows how to program the PLL. NOTE: The round function in the following equations means that the real number should be rounded to the nearest integer number. 1. Choose the desired bus frequency ...

Page 107

... Freescale Semiconductor, Inc. 4. Select a VCO frequency multiplier < Calculate and verify the adequacy of the VCO and bus 7. Select the VCO’s power-of-two range multiplier E, according to MC68HC908GR8 — Rev 4.0 MOTOROLA For More Information On This Product, allows. See Electrical Specifications. Choose the reference divider ...

Page 108

... Freescale Semiconductor, Inc. Clock Generator Module (CGMC) 8. Select a VCO linear range multiplier, L, where f 9. Calculate and verify the adequacy of the VCO programmed 10. Verify the choice and L by comparing f NOTE: Exceeding the recommended maximum bus frequency or VCO frequency can crash the MCU. ...

Page 109

... Freescale Semiconductor, Inc. Table 7-1 notation): 2.4576 MHz 4.9152 MHz 7.3728 MHz 7.4.7 Special Programming Exceptions The programming method described in account for three possible exceptions. A value of 0 for meaningless when used in the equations given. To account for these exceptions: • • (See Base Clock Selector MC68HC908GR8 — ...

Page 110

... Freescale Semiconductor, Inc. Clock Generator Module (CGMC) 7.4.8 Base Clock Selector Circuit This circuit is used to select either the crystal clock, CGMXCLK, or the VCO clock, CGMVCLK, as the source of the base clock, CGMOUT. The two input clocks go through a transition control circuit that waits up to three CGMXCLK cycles and three CGMVCLK cycles to change from one clock source to the other ...

Page 111

... Freescale Semiconductor, Inc. The series resistor (R oscillator guidelines. Refer to the crystal manufacturer’s data for more information regarding values for C1 and C2. Figure 7-2 • • Routing should be done with great care to minimize signal cross talk and noise. See CGM Component Specifications ...

Page 112

... Freescale Semiconductor, Inc. Clock Generator Module (CGMC) 7.5 I/O Signals The following paragraphs describe the CGMC I/O signals. 7.5.1 Crystal Amplifier Input Pin (OSC1) The OSC1 pin is an input to the crystal oscillator amplifier. 7.5.2 Crystal Amplifier Output Pin (OSC2) The OSC2 pin is the output of the crystal oscillator inverting amplifier. ...

Page 113

... Freescale Semiconductor, Inc. 7.5.6 Oscillator Enable Signal (SIMOSCEN) The SIMOSCEN signal comes from the system integration module (SIM) and enables the oscillator and PLL. 7.5.7 Oscillator Stop Mode Enable Bit (OSCSTOPENB) OSCSTOPENB is a bit in the CONFIG register that enables the oscillator to continue operating during stop mode ...

Page 114

... Freescale Semiconductor, Inc. Clock Generator Module (CGMC) 7.6 CGMC Registers These registers control and monitor operation of the CGMC: • • • • • • Figure 7-3 Addr. Register Name Read: PLL Control Register $0036 Write: (PCTL) Reset: Read: PLL Bandwidth Control ...

Page 115

... Freescale Semiconductor, Inc. Read: PLL VCO Select Range $003A Write: Register (PMRS) Reset: Read: PLL Reference Divider $003B Write: Select Register (PMDS) Reset: NOTES: 1. When AUTO = 0, PLLIE is forced clear and is read-only. 2. When AUTO = 0, PLLF and LOCK read as clear. 3. When AUTO = 1, ACQ is read-only. ...

Page 116

... Freescale Semiconductor, Inc. Clock Generator Module (CGMC PLL interrupts enabled 0 = PLL interrupts disabled PLLF — PLL Interrupt Flag Bit This read-only bit is set whenever the LOCK bit toggles. PLLF generates an interrupt request if the PLLIE bit also is set. PLLF always reads as logic 0 when the AUTO bit in the PLL bandwidth control register (PBWC) is clear ...

Page 117

... Freescale Semiconductor, Inc. is set, and BCS cannot be set when PLLON is clear. If the PLL is off (PLLON = 0), selecting CGMVCLK requires two writes to the PLL control register. (See PRE1 and PRE0 — Prescaler Program Bits These read/write bits control a prescaler that selects the prescaler power-of-two multiplier, P ...

Page 118

... Freescale Semiconductor, Inc. Clock Generator Module (CGMC) 7.6.2 PLL Bandwidth Control Register The PLL bandwidth control register (PBWC): • • • • Address: Read: Write: Reset: AUTO — Automatic Bandwidth Control Bit This read/write bit selects automatic or manual bandwidth control. When initializing the PLL for manual operation (AUTO = 0), clear the ACQ bit before turning on the PLL ...

Page 119

... Freescale Semiconductor, Inc VCO frequency correct or locked 0 = VCO frequency incorrect or unlocked ACQ — Acquisition Mode Bit When the AUTO bit is set, ACQ is a read-only bit that indicates whether the PLL is in acquisition mode or tracking mode. When the AUTO bit is clear, ACQ is a read/write bit that controls whether the PLL is in acquisition or tracking mode ...

Page 120

... Freescale Semiconductor, Inc. Clock Generator Module (CGMC) NOTE: The multiplier select bits have built-in protection such that they cannot be written when the PLL is on (PLLON = 1). PMSH[7:4] — Unimplemented Bits These bits have no function and always read as logic 0s. 7.6.4 PLL Multiplier Select Register Low The PLL multiplier select register low (PMSL) contains the programming information for the low byte of the modulo feedback divider ...

Page 121

... Freescale Semiconductor, Inc. 7.6.5 PLL VCO Range Select Register NOTE: PMRS may be called PVRS on other HC08 derivatives. The PLL VCO range select register (PMRS) contains the programming information required for the hardware configuration of the VCO. Address: Read: Write: Reset: VRS7–VRS0 — VCO Range Select Bits ...

Page 122

... Freescale Semiconductor, Inc. Clock Generator Module (CGMC) 7.6.6 PLL Reference Divider Select Register NOTE: PMDS may be called PRDS on other HC08 derivatives. The PLL reference divider select register (PMDS) contains the programming information for the modulo reference divider. Address: Read: Write: Reset: Figure 7-9. PLL Reference Divider Select Register (PMDS) RDS3– ...

Page 123

... Freescale Semiconductor, Inc. 7.7 Interrupts When the AUTO bit is set in the PLL bandwidth control register (PBWC), the PLL can generate a CPU interrupt request every time the LOCK bit changes state. The PLLIE bit in the PLL control register (PCTL) enables CPU interrupts from the PLL. PLLF, the interrupt flag in the PCTL, becomes set whether interrupts are enabled or not ...

Page 124

... Freescale Semiconductor, Inc. Clock Generator Module (CGMC) mode, such as when the PLL is first enabled and waiting for LOCK or LOCK is lost. 7.8.2 Stop Mode If the OSCSTOPENB bit in the CONFIG register is cleared (default), then the STOP instruction disables the CGMC (oscillator and phase locked loop) and holds low all CGMC outputs (CGMXCLK, CGMOUT, and CGMINT) ...

Page 125

... Freescale Semiconductor, Inc. 7.9 Acquisition/Lock Time Specifications The acquisition and lock times of the PLL are, in many applications, the most critical PLL design parameters. Proper design and use of the PLL ensures the highest stability and lowest acquisition/lock times. 7.9.1 Acquisition/Lock Time Definitions Typical control systems refer to the acquisition time or lock time as the reaction time, within specified tolerances, of the system to a step input ...

Page 126

... Freescale Semiconductor, Inc. Clock Generator Module (CGMC) The most critical parameter which affects the reaction times of the PLL is the reference frequency, f detector and controls how often the PLL makes corrections. For stability, the corrections must be small compared to the desired frequency, so several corrections are required to reduce the frequency error. ...

Page 127

... Freescale Semiconductor, Inc. 7.9.3 Choosing a Filter As described in filter network is critical to the stability and reaction time of the PLL. The PLL is also dependent on reference frequency and supply voltage. Either of the filter networks in a 32.768-kHz reference crystal. In low-cost applications, where stability and reaction time of the PLL is not critical, this filter network can be replaced by a single capacitor. MC68HC908GR8 — ...

Page 128

... Freescale Semiconductor, Inc. Clock Generator Module (CGMC) Technical Data 128 For More Information On This Product, Clock Generator Module (CGMC) Go to: www.freescale.com MC68HC908GR8 — Rev 4.0 MOTOROLA ...

Page 129

... Freescale Semiconductor, Inc. Technical Data — MC68HC908GR8 Section 8. Configuration Register (CONFIG) 8.1 Contents 8.2 8.3 8.2 Introduction This section describes the configuration registers, CONFIG1 and CONFIG2. The configuration registers enable or disable these options: • • • • • • 8.3 Functional Description The configuration registers are used in the initialization of various options ...

Page 130

... Freescale Semiconductor, Inc. Configuration Register (CONFIG) NOTE: To ensure correct operation of the MCU under all operating conditions, the user must write data $1C to address $0033 immediately after reset. This is to ensure proper termination of an unused module within the MCU. NOTE FLASH device, the options except LVI5OR3 are one-time writeable by the user after each reset ...

Page 131

... Freescale Semiconductor, Inc. OSCSTOPENB— Oscillator Stop Mode Enable Bar Bit OSCSTOPENB enables the oscillator to continue operating during stop mode. Setting the OSCSTOPENB bit allows the oscillator to operate continuously even during stop mode. This is useful for driving the timebase module to allow it to generate periodic wakeup while in stop mode ...

Page 132

... Freescale Semiconductor, Inc. Configuration Register (CONFIG) LVI5OR3 — LVI Operating Mode Bit LVI5OR3 selects the voltage operating mode of the LVI module. See Low-Voltage Inhibit should match the operating V LVI’s voltage trip points for each of the modes LVI operates in 5V mode. ...

Page 133

... Freescale Semiconductor, Inc. Technical Data — MC68HC908GR8 Section 9. Computer Operating Properly (COP) 9.1 Contents 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 9.2 Introduction The computer operating properly (COP) module contains a free-running counter that generates a reset if allowed to overflow. The COP module helps software recover from runaway code ...

Page 134

... Freescale Semiconductor, Inc. Computer Operating Properly (COP) CGMXCLK STOP INSTRUCTION INTERNAL RESET SOURCES RESET VECTOR FETCH COPCTL WRITE COPEN (FROM SIM) COP DISABLE (FROM CONFIG) RESET COPCTL WRITE COP RATE SEL (FROM CONFIG) The COP counter is a free-running 6-bit counter preceded by a 12-bit prescaler counter ...

Page 135

... Freescale Semiconductor, Inc. In monitor mode, the COP is disabled if the RST pin or the IRQ1 is held at V TST NOTE: Place COP clearing instructions in the main program and not in an interrupt subroutine. Such an interrupt subroutine could keep the COP from generating a reset even while the main program is not working properly ...

Page 136

... Freescale Semiconductor, Inc. Computer Operating Properly (COP) 9.4.6 Reset Vector Fetch A reset vector fetch occurs when the vector address appears on the data bus. A reset vector fetch clears the COP prescaler. 9.4.7 COPD (COP Disable) The COPD signal reflects the state of the COP disable bit (COPD) in the configuration register ...

Page 137

... Freescale Semiconductor, Inc. 9.7 Monitor Mode When monitor mode is entered with V disabled as long as V monitor mode is entered by having blank reset vectors and not having V on the IRQ pin, the COP is automatically disabled until a POR TST occurs. 9.8 Low-Power Modes The WAIT and STOP instructions put the MCU in low power- consumption standby modes ...

Page 138

... Freescale Semiconductor, Inc. Computer Operating Properly (COP) Technical Data 138 For More Information On This Product, Computer Operating Properly (COP) Go to: www.freescale.com MC68HC908GR8 — Rev 4.0 MOTOROLA ...

Page 139

... Freescale Semiconductor, Inc. Technical Data — MC68HC908GR8 Section 10. Central Processing Unit (CPU) 10.1 Contents 10.2 10.3 10.4 10.5 10.6 10.7 10.8 10.9 10.2 Introduction The M68HC08 CPU (central processor unit enhanced and fully object-code-compatible version of the M68HC05 CPU. The CPU08 Reference Manual (Motorola document order number CPU08RM/AD) contains a description of the CPU instruction set, addressing modes, and architecture ...

Page 140

... Freescale Semiconductor, Inc. Central Processing Unit (CPU) • • • • • • • 10.4 CPU registers Figure 10-1 the memory map. Technical Data 140 For More Information On This Product, 64K byte program/data memory space 16 addressing modes Memory-to-memory data moves without using accumulator ...

Page 141

... Freescale Semiconductor, Inc. 10.4.1 Accumulator (A) The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operations. Read: A Write: Reset: 10.4.2 Index register (H:X) The 16-bit index register allows indexed addressing of a 64K byte memory space the upper byte of the index register and X is the lower byte ...

Page 142

... Freescale Semiconductor, Inc. Central Processing Unit (CPU) 10.4.3 Stack pointer (SP) The stack pointer is a 16-bit register that contains the address of the next location on the stack. During a reset, the stack pointer is preset to $00FF. The reset stack pointer (RSP) instruction sets the least significant byte to $FF and does not affect the most significant byte ...

Page 143

... Freescale Semiconductor, Inc. During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF. The vector address is the address of the first instruction to be executed after exiting the reset state. Bit 15 Read: PC Write: Reset: 10.4.5 Condition code register (CCR) The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed ...

Page 144

... Freescale Semiconductor, Inc. Central Processing Unit (CPU) The CPU sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an ADD or ADC operation. The half- carry flag is required for binary-coded decimal (BCD) arithmetic operations. The DAA instruction uses the states of the H and C flags to determine the appropriate correction factor ...

Page 145

... Freescale Semiconductor, Inc. N — Negative flag The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result Negative result 0 = Non-negative result Z — Zero flag The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00 ...

Page 146

... Freescale Semiconductor, Inc. Central Processing Unit (CPU) 10.6.1 WAIT mode The WAIT instruction: • • 10.6.2 STOP mode The STOP instruction: • • After exiting STOP mode, the CPU clock begins running after the oscillator stabilization delay. 10.7 CPU during break interrupts ...

Page 147

... Freescale Semiconductor, Inc. 10.8 Instruction Set Summary Table 10-1 Table 10-1. Instruction Set Summary Source Operation Form ADC #opr ADC opr ADC opr ADC opr,X Add with Carry ADC opr,X ADC ,X ADC opr,SP ADC opr,SP ADD #opr ADD opr ADD opr ...

Page 148

... Freescale Semiconductor, Inc. Central Processing Unit (CPU) Table 10-1. Instruction Set Summary (Continued) Source Operation Form BCLR n, opr Clear Bit BCS rel Branch if Carry Bit Set (Same as BLO) BEQ rel Branch if Equal Branch if Greater Than or Equal To BGE opr (Signed Operands) Branch if Greater Than (Signed ...

Page 149

... Freescale Semiconductor, Inc. Table 10-1. Instruction Set Summary (Continued) Source Operation Form BNE rel Branch if Not Equal BPL rel Branch if Plus BRA rel Branch Always BRCLR n,opr,rel Branch if Bit Clear BRN rel Branch Never BRSET n,opr,rel Branch if Bit Set BSET n,opr ...

Page 150

... Freescale Semiconductor, Inc. Central Processing Unit (CPU) Table 10-1. Instruction Set Summary (Continued) Source Operation Form CMP #opr CMP opr CMP opr CMP opr,X Compare A with M CMP opr,X CMP ,X CMP opr,SP CMP opr,SP COM opr COMA COMX Complement (One’s Complement) ...

Page 151

... Freescale Semiconductor, Inc. Table 10-1. Instruction Set Summary (Continued) Source Operation Form INC opr INCA INCX Increment INC opr,X INC ,X INC opr,SP JMP opr JMP opr JMP opr,X Jump JMP opr,X JMP ,X JSR opr JSR opr JSR opr,X Jump to Subroutine JSR opr,X ...

Page 152

... Freescale Semiconductor, Inc. Central Processing Unit (CPU) Table 10-1. Instruction Set Summary (Continued) Source Operation Form NEG opr NEGA NEGX Negate (Two’s Complement) NEG opr,X NEG ,X NEG opr,SP NOP No Operation NSA Nibble Swap A ORA #opr ORA opr ORA opr ORA opr,X ...

Page 153

... Freescale Semiconductor, Inc. Table 10-1. Instruction Set Summary (Continued) Source Operation Form SBC #opr SBC opr SBC opr SBC opr,X Subtract with Carry SBC opr,X SBC ,X SBC opr,SP SBC opr,SP SEC Set Carry Bit SEI Set Interrupt Mask STA opr STA opr ...

Page 154

... Freescale Semiconductor, Inc. Central Processing Unit (CPU) Table 10-1. Instruction Set Summary (Continued) Source Operation Form TST opr TSTA TSTX Test for Negative or Zero TST opr,X TST ,X TST opr,SP TSX Transfer SP to H:X TXA Transfer TXS Transfer H Accumulatorn C Carry/borrow bitopr CCRCondition code registerPC ...

Page 155

... Freescale Semiconductor, Inc. Central Processing Unit (CPU) Technical Data 155 For More Information On This Product, Central Processing Unit (CPU) Go to: www.freescale.com MC68HC908GR8 — Rev 4.0 MOTOROLA ...

Page 156

... Freescale Semiconductor, Inc. Central Processing Unit (CPU) Technical Data 156 For More Information On This Product, Central Processing Unit (CPU) Go to: www.freescale.com MC68HC908GR8 — Rev 4.0 MOTOROLA ...

Page 157

... Freescale Semiconductor, Inc. Technical Data — MC68HC908GR8 11.1 Contents 11.2 11.3 11.4 11.5 11.6 11.7 11.8 11.9 11.10 STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 11.2 Introduction This section describes the operation of the embedded FLASH memory. This memory can be read, programmed, and erased from a single external supply ...

Page 158

... Freescale Semiconductor, Inc. Flash Memory Register (FLCR). Details for these operations appear later in this section. The FLASH is organized internally as a 8192-word by 8-bit CMOS page erase, byte (8-bit) program Embedded Flash Memory. Each page consists of 64 bytes. The page erase operation erases all words within a page ...

Page 159

... Freescale Semiconductor, Inc. 11.4 FLASH Control Register The FLASH control register (FLCR) controls FLASH program and erase operations. Address: Read: Write: Reset: HVEN — High-Voltage Enable Bit This read/write bit enables the charge pump to drive high voltages for program and erase operations in the array. HVEN can only be set if either PGM = 1 or ERASE = 1 and the proper sequence for program or erase is followed ...

Page 160

... Freescale Semiconductor, Inc. Flash Memory PGM — Program Control Bit This read/write bit configures the memory for program operation. PGM is interlocked with the ERASE bit such that both bits cannot be equal set the same time Program operation selected 0 = Program operation unselected 11 ...

Page 161

... Freescale Semiconductor, Inc. 11.6 FLASH Mass Erase Operation Use this step-by-step procedure to erase entire FLASH memory to read as logic 1: 1. Set both the ERASE bit, and the MASS bit in the FLASH control 2. Read from the FLASH block protect register. 3. Write any data to any FLASH address* within the FLASH memory 4 ...

Page 162

... Freescale Semiconductor, Inc. Flash Memory 11.7 FLASH Program/Read Operation Programming of the FLASH memory is done on a row basis. A row consists of 32 consecutive bytes starting from addresses $XX00, $XX20, $XX40, $XX60, $XX80, $XXA0, $XXC0, and $XXE0. Use this step-by-step procedure to program a row of FLASH memory ...

Page 163

... Freescale Semiconductor, Inc. NOTE: Programming and erasing of FLASH locations cannot be performed by code being executed from the FLASH memory. While these operations must be performed in the order shown, other unrelated operations may occur between the steps. Do not exceed t Characteristics. 11.8 FLASH Block Protection ...

Page 164

... Freescale Semiconductor, Inc. Flash Memory Algorithm for programming a row (32 bytes) of FLASH memory NOTE: The time between each FLASH address change (step 7 to step 7), or the time between the last FLASH address programmed to clearing PGM bit (step 7 to step 10) must not exceed the maximum programming time, t max ...

Page 165

... Freescale Semiconductor, Inc. 11.8.1 FLASH Block Protect Register The FLASH block protect register (FLBPR) is implemented as a byte within the FLASH memory, and therefore can only be written during a programming sequence of the FLASH memory. The value in this register determines the starting location of the protected range within the FLASH memory ...

Page 166

... Freescale Semiconductor, Inc. Flash Memory Examples of protect start address: $81 (1000 0001) $82 (1000 0010) $FE (1111 1110) 11.9 Wait Mode Putting the MCU into wait mode while the FLASH is in read mode does not affect the operation of the FLASH memory directly, but there will not be any memory activity since the CPU is inactive ...

Page 167

... Freescale Semiconductor, Inc. Technical Data — MC68HC908GR8 12.1 Contents 12.2 12.3 12.4 12.5 12.6 12.7 12.2 Introduction The IRQ (external interrupt) module provides a maskable interrupt input. 12.3 Features Features of the IRQ module include: • • • • • • MC68HC908GR8 — Rev 4.0 ...

Page 168

... Freescale Semiconductor, Inc. External Interrupt (IRQ) 12.4 Functional Description A logic 0 applied to the external interrupt pin can latch a CPU interrupt request. Interrupt signals on the IRQ1 pin are latched into the IRQ latch. An interrupt latch remains set until one of the following actions occurs: • ...

Page 169

... Freescale Semiconductor, Inc. NOTE: The interrupt mask (I) in the condition code register (CCR) masks all interrupt requests, including external interrupt requests. ACK RESET VECTOR FETCH DECODER V DD INTERNAL V DD PULLUP DEVICE IRQ1 MODE Figure 12-1. IRQ Module Block Diagram Addr. Register Name ...

Page 170

... Freescale Semiconductor, Inc. External Interrupt (IRQ) 12.5 IRQ1 Pin A logic 0 on the IRQ1 pin can latch an interrupt request into the IRQ latch. A vector fetch, software clear, or reset clears the IRQ latch. If the MODE bit is set, the IRQ1 pin is both falling-edge-sensitive and low-level-sensitive ...

Page 171

... Freescale Semiconductor, Inc. The IRQF bit in the INTSCR register can be used to check for pending interrupts. The IRQF bit is not affected by the IMASK bit, which makes it useful in applications where polling is preferred. Use the BIH or BIL instruction to read the logic level on the IRQ1 pin. ...

Page 172

... Freescale Semiconductor, Inc. External Interrupt (IRQ) 12.7 IRQ Status and Control Register The IRQ status and control register (INTSCR) controls and monitors operation of the IRQ module. The INTSCR: • • • • Address: Read: Write: Reset: Figure 12-3. IRQ Status and Control Register (INTSCR) IRQF — ...

Page 173

... Freescale Semiconductor, Inc. MODE — IRQ Edge/Level Select Bit This read/write bit controls the triggering sensitivity of the IRQ1 pin. Reset clears MODE IRQ1 interrupt requests on falling edges and low levels 0 = IRQ1 interrupt requests on falling edges only MC68HC908GR8 — Rev 4.0 MOTOROLA ...

Page 174

... Freescale Semiconductor, Inc. External Interrupt (IRQ) Technical Data 174 For More Information On This Product, External Interrupt (IRQ) Go to: www.freescale.com MC68HC908GR8 — Rev 4.0 MOTOROLA ...

Page 175

... Freescale Semiconductor, Inc. Technical Data — MC68HC908GR8 13.1 Contents 13.2 13.3 13.4 13.5 13.6 13.7 13.8 13.2 Introduction The keyboard interrupt module (KBI) provides four independently maskable external interrupts. 13.3 Features • • • • • MC68HC908GR8 — Rev 4.0 MOTOROLA For More Information On This Product, Section 13 ...

Page 176

... Freescale Semiconductor, Inc. Keyboard Interrupt (KBI) 13.4 Functional Description Writing to the KBIE3–KBIE0 bits in the keyboard interrupt enable register independently enables or disables each port A pin as a keyboard interrupt pin. Enabling a keyboard interrupt pin also enables its internal pullup device. A logic 0 applied to an enabled keyboard interrupt pin latches a keyboard interrupt request ...

Page 177

... Freescale Semiconductor, Inc. KBD0 . TO PULLUP ENABLE . KB0IE . KBD3 TO PULLUP ENABLE KB3IE Figure 13-1. Keyboard Module Block Diagram Addr. Register Name Read: Keyboard Status $001A and Control Register Write: (INTKBSCR) Reset: Read: Keyboard Interrupt Enable $001B Write: Register (INTKBIER) Reset: Figure 13-2. I/O Register Summary MC68HC908GR8 — ...

Page 178

... Freescale Semiconductor, Inc. Keyboard Interrupt (KBI) If the MODEK bit is set, the keyboard interrupt pins are both falling edge- and low-level sensitive, and both of the following actions must occur to clear a keyboard interrupt request: • • The vector fetch or software clear and the return of all enabled keyboard interrupt pins to logic 1 may occur in any order ...

Page 179

... Freescale Semiconductor, Inc. NOTE: Setting a keyboard interrupt enable bit (KBIEx) forces the corresponding keyboard interrupt pin input, overriding the data direction register. However, the data direction register bit must be a logic 0 for software to read the pin. 13.5 Keyboard Initialization When a keyboard interrupt pin is enabled, it takes time for the internal pullup to reach a logic 1 ...

Page 180

... Freescale Semiconductor, Inc. Keyboard Interrupt (KBI) 13.6 Low-Power Modes The WAIT and STOP instructions put the MCU in low power- consumption standby modes. 13.6.1 Wait Mode The keyboard module remains active in wait mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of wait mode ...

Page 181

... Freescale Semiconductor, Inc. 13.8 I/O Registers These registers control and monitor operation of the keyboard module: • • 13.8.1 Keyboard Status and Control Register The keyboard status and control register: • • • • Address: $001A Read: Write: Reset: Figure 13-3. Keyboard Status and Control Register (INTKBSCR) Bits 7– ...

Page 182

... Freescale Semiconductor, Inc. Keyboard Interrupt (KBI) ACKK — Keyboard Acknowledge Bit Writing a logic 1 to this write-only bit clears the keyboard interrupt request. ACKK always reads as logic 0. Reset clears ACKK. IMASKK — Keyboard Interrupt Mask Bit Writing a logic 1 to this read/write bit prevents the output of the keyboard interrupt mask from generating interrupt requests ...

Page 183

... Freescale Semiconductor, Inc. Technical Data — MC68HC908GR8 14.1 Contents 14.2 14.3 14.4 14.5 14.6 14.7 14.2 Introduction This section describes the low-voltage inhibit (LVI) module, which monitors the voltage on the V voltage falls below the LVI trip falling voltage, V 14.3 Features Features of the LVI module include: • ...

Page 184

... Freescale Semiconductor, Inc. Low-Voltage Inhibit (LVI) 14.4 Functional Description Figure 14-1 out of reset. The LVI module contains a bandgap reference circuit and comparator. Clearing the LVI power disable bit, LVIPWRD, enables the LVI to monitor V enables the LVI module to generate a reset when V point voltage, V enables the LVI to operate in stop mode ...

Page 185

... Freescale Semiconductor, Inc. LVISTOP, LVIPWRD, LVI5OR3, and LVIRSTD are in the configuration register (MOR1). See LVI’s configuration bits. Once an LVI reset occurs, the MCU remains in reset until V exit reset. See interaction between the SIM and the LVI. The output of the comparator controls the state of the LVIOUT flag in the LVI status register (LVISR) ...

Page 186

... Freescale Semiconductor, Inc. Low-Voltage Inhibit (LVI) Addr. Register Name Read: LVIOUT LVI Status Register $FE0C Write: (LVISR) Reset: Figure 14-2. LVI I/O Register Summary 14.4.1 Polled LVI Operation In applications that can operate at V software can monitor V register, the LVIPWRD bit must be at logic 0 to enable the LVI module, and the LVIRSTD bit must be at logic 1 to disable LVI resets ...

Page 187

... Freescale Semiconductor, Inc. 14.4.4 LVI Trip Selection The LVI5OR3 bit in the configuration register selects whether the LVI is configured for protection. NOTE: The microcontroller is guaranteed to operate at a minimum supply voltage. The trip point (V this. (See 14.5 LVI Status Register The LVI status register (LVISR) indicates if the V ...

Page 188

... Freescale Semiconductor, Inc. Low-Voltage Inhibit (LVI) 14.6 LVI Interrupts The LVI module does not generate interrupt requests. 14.7 Low-Power Modes The STOP and WAIT instructions put the MCU in low power- consumption standby modes. 14.7.1 Wait Mode If enabled, the LVI module remains active in wait mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of wait mode ...

Page 189

... Freescale Semiconductor, Inc. Technical Data — MC68HC908GR8 15.1 Contents 15.2 15.3 15.4 15.5 15.2 Introduction This section describes the monitor ROM (MON) and the monitor mode entry methods. The monitor ROM allows complete testing of the MCU through a single-wire interface with a host computer. Monitor mode entry ...

Page 190

... Freescale Semiconductor, Inc. Monitor ROM (MON) • • • • • • 15.4 Functional Description The monitor ROM receives and executes commands from a host computer. mode and communicate with a host computer via a standard RS-232 interface. Simple monitor commands can access any memory address. In monitor mode, the MCU can execute code downloaded into RAM by a host computer while most MCU pins retain normal operating mode functions ...

Page 191

... Freescale Semiconductor, Inc. 1 MC145407 + DB- Notes: 1. SW2, SW3, and SW4: Position C — Enter monitor mode using external oscillator. SW2, SW3, and SW4: Position D — Enter monitor mode using external XTAL and internal PLL. 2. See . Monitor Mode Signal Requirements and Options MC68HC908GR8 — Rev 4.0 ...

Page 192

... Freescale Semiconductor, Inc. Monitor ROM (MON) The monitor code has been updated from previous versions to allow enabling the PLL to generate the internal clock, provided the reset vector is blank, when the device is being clocked by a low-frequency crystal. This addition, which is enabled when IRQ is held low out of rest, is ...

Page 193

... Freescale Semiconductor, Inc. Table 15-1. Monitor Mode Signal Requirements and Options $FFFE/ IRQ RESET PLL PTB0 PTB1 $FFFF X GND OFF 1 TST V TST V V $FFFF OFF GND $FFFF $FFFF OFF X TST GND Not or OFF X or $FFFF V GND TST Notes: 1. External clock is derived by a 32.768 kHz crystal or a 9.8304 MHz off-chip oscillator 2. PTA0 = 1 if serial communication ...

Page 194

... Freescale Semiconductor, Inc. Monitor ROM (MON) requirements and conditions, are not in effect. This is to reduce circuit requirements when performing in-circuit programming. NOTE: If the reset vector is blank and monitor mode is entered, the chip will see an additional reset cycle after the initial POR reset. Once the part has been programmed, the traditional method of applying a voltage, V IRQ must be used to enter monitor mode ...

Page 195

... Freescale Semiconductor, Inc. Figure 15-2. Low-Voltage Monitor Mode Entry Flowchart Enter monitor mode with pin configuration shown in pulling RST low and then high. The rising edge of RST latches monitor mode. Once monitor mode is latched, the values on the specified pins can change. ...

Page 196

... Freescale Semiconductor, Inc. Monitor ROM (MON) Table 15-2 mode. Modes User Monitor 15.4.2 Data Format Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format. Transmit and receive baud rates must be identical. START BIT 15.4.3 Break Signal A start bit (logic 0) followed by nine logic 0 bits is a break signal. When the monitor receives a break signal, it drives the PTA0 pin high for the duration of two bits and then echoes back the break signal ...

Page 197

... Freescale Semiconductor, Inc. 15.4.4 Baud Rate The communication baud rate is controlled by the crystal frequency upon entry into monitor mode. The divide by ratio is 1024. If monitor mode was entered with V also set at 1024. If monitor mode was entered with V internal PLL steps up the external frequency, presumed to be 32.768 kHz ...

Page 198

... Freescale Semiconductor, Inc. Monitor ROM (MON) The monitor ROM firmware echoes each received byte back to the PTA0 pin for error checking. An 11-bit delay at the end of each command allows the host to send a break character to cancel the command. A delay of two bit times occurs before each echo and before READ, IREAD, or READSP data is returned ...

Page 199

... Freescale Semiconductor, Inc. A brief description of each monitor mode command is given in 4 through Description Operand Data Returned Opcode SENT TO MONITOR ECHO Description Operand Data Returned Opcode FROM HOST WRITE ECHO MC68HC908GR8 — Rev 4.0 MOTOROLA For More Information On This Product, Table 15-9. ...

Page 200

... Freescale Semiconductor, Inc. Monitor ROM (MON) Description Operand Data Returned Opcode Description Operand Data Returned Opcode Technical Data 200 For More Information On This Product, Table 15-6. IREAD (Indexed Read) Command Read next 2 bytes in memory from last address accessed 2-byte address in high byte:low byte order ...

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