R5F21217JFP Renesas Electronics America, R5F21217JFP Datasheet
R5F21217JFP
Specifications of R5F21217JFP
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R5F21217JFP Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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R8C/20 Group, 16 R8C/21 Group Hardware Manual RENESAS MCU R8C FAMILY / R8C/2x SERIES All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change ...
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This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in ...
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General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If ...
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How to Use This Manual 1. Purpose and Target Readers This manual is designed to provide the user with an understanding of the hardware functions and electrical characteristics of the MCU intended for users designing application systems incorporating ...
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Notation of Numbers and Symbols The notation conventions for register names, bit names, numbers, and symbols used in this manual are described below. (1) Register Names, Bit Names, and Pin Names Registers, bits, and pins are referred to in ...
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Register Notation The symbols and terms used in register diagrams are described below. XXX Register Bit Symbol XXX0 XXX1 XXX4 XXX5 XXX6 XXX7 *1 Blank: Set ...
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List of Abbreviations and Acronyms Abbreviation ACIA bps CRC DMA DMAC GSM Hi-Z IEBus I/O IrDA LSB MSB NC PLL PWM SIM UART VCO All trademarks and registered trademarks are the property of their respective owners. All trademarks and ...
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SFR Page Reference ........................................................................................................................... Overview ......................................................................................................................................... 1 1.1 Applications ............................................................................................................................................... 1 1.2 Performance Overview .............................................................................................................................. 2 1.3 Block Diagram .......................................................................................................................................... 4 1.4 Product Information .................................................................................................................................. 5 1.5 Pin Assignments ........................................................................................................................................ 7 1.6 Pin Functions ............................................................................................................................................. 8 ...
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Monitoring Vdet2 ............................................................................................................................... 34 6.2 Voltage Monitor 1 Reset ......................................................................................................................... 35 6.3 Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset ..................................................................... 36 7. Programmable I/O Ports ............................................................................................................... 38 7.1 Functions of Programmable I/O Ports ..................................................................................................... 38 7.2 Effect ...
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Peripheral Function Interrupt .............................................................................................................. 89 12.1.5 Interrupts and Interrupt Vector ........................................................................................................... 90 12.1.6 Interrupt Control ................................................................................................................................. 92 12.2 INT Interrupt ......................................................................................................................................... 101 12.2.1 INTi Interrupt ( .................................................................................................................. 101 12.2.2 INTi Input Filter ( ...
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Output Compare Mode ..................................................................................................................... 258 14.4.2 Notes on Timer RE ........................................................................................................................... 264 15. Serial Interface ............................................................................................................................ 265 15.1 Clock Synchronous Serial I/O Mode ..................................................................................................... 271 15.1.1 Polarity Select Function .................................................................................................................... 274 15.1.2 LSB First/MSB First Select Function ............................................................................................... 274 ...
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A/D Conversion Cycles ......................................................................................................................... 371 18.5 Internal Equivalent Circuit of Analog Input .......................................................................................... 372 18.6 Output Impedance of Sensor Under A/D Conversion ........................................................................... 373 18.7 Notes on A/D Converter ........................................................................................................................ 374 19. Flash Memory ............................................................................................................................. 375 19.1 Overview ............................................................................................................................................... ...
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Notes on Flash Memory ........................................................................................................................ 448 21.8.1 CPU Rewrite Mode ........................................................................................................................... 448 21.9 Notes on Noise ...................................................................................................................................... 451 21.9.1 Inserting a Bypass Capacitor between VCC and VSS Pins as a Countermeasure against Noise and Latch-up ............................................................................................................................................ 451 21.9.2 Countermeasures ...
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SFR Page Reference Address Register 0000h 0001h 0002h 0003h 0004h Processor Mode Register 0 0005h Processor Mode Register 1 0006h System Clock Control Register 0 0007h System Clock Control Register 1 0008h 0009h 000Ah Protect Register 000Bh 000Ch Oscillation Stop ...
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Address Register 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h 0089h 008Ah 008Bh 008Ch 008Dh 008Eh 008Fh 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009Ah 009Bh 009Ch 009Dh 009Eh 009Fh 00A0h UART0 Transmit/Receive Mode Register 00A1h ...
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Address Register 0100h Timer RA Control Register 0101h Timer RA I/O Control Register 0102h Timer RA Mode Register 0103h Timer RA Prescaler Register 0104h Timer RA Register 0105h 0106h LIN Control Register 0107h LIN Status Register 0108h Timer RB Control ...
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R8C/20 Group, R8C/21 Group RENESAS MCU 1. Overview This MCU is built using the high-performance silicon gate CMOS process using the R8C CPU core and is packaged in a 48-pin plastic molded LQFP. This MCU operates using sophisticated instructions featuring ...
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R8C/20 Group, R8C/21 Group 1.2 Performance Overview Table 1.1 outlines the Functions and Specifications for R8C/20 Group and Table 1.2 outlines the Functions and Specifications for R8C/21 Group. Table 1.1 Functions and Specifications for R8C/20 Group Item CPU Number of ...
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R8C/20 Group, R8C/21 Group Table 1.2 Functions and Specifications for R8C/21 Group Item CPU Number of fundamental instructions 89 instructions Minimum instruction execution time 50 ns (f(XIN MHz, VCC = 3.0 to 5.5 V) Operating mode Address space ...
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R8C/20 Group, R8C/21 Group 1.3 Block Diagram Figure 1.1 shows a Block Diagram. I/O port Timer Timer RA (8 bits) Timer RB (8 bits) × 2 channels Timer RD (16 bits Timer RE (8 bits) Watchdog timer (15 bits) Figure ...
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R8C/20 Group, R8C/21 Group 1.4 Product Information Table 1.3 lists Product Information for R8C/20 Group and Table 1.4 lists Product Information for R8C/21 Group. Table 1.3 Product Information for R8C/20 Group Type No. ROM Capacity R5F21206JFP 32 Kbytes R5F21207JFP 48 ...
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... R8C/20 Group, R8C/21 Group Table 1.4 Product Information for R8C/21 Group Type No. Program ROM R5F21216JFP 32 Kbytes R5F21217JFP 48 Kbytes R5F21218JFP 64 Kbytes R5F2121AJFP 96 Kbytes R5F2121CJFP 128 Kbytes R5F21216KFP 32 Kbytes R5F21217KFP 48 Kbytes R5F21218KFP 64 Kbytes R5F2121AKFP 96 Kbytes R5F2121CKFP 128 Kbytes NOTE not use addresses 20000h to 23FFFh because these areas are used for the emulator debugger. ...
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R8C/20 Group, R8C/21 Group 1.5 Pin Assignments Figure 1.4 shows Pin Assignments (Top View). Pin assignments (top view) P0_6/AN1 37 P0_5/AN2 38 P0_4/AN3 39 P4_2/VREF 40 P6_0/TREO 41 P6_2 42 P6_1 43 P0_3/AN4 44 P0_2/AN5 45 P0_1/AN6 46 P0_0/AN7 47 ...
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R8C/20 Group, R8C/21 Group 1.6 Pin Functions Table 1.5 lists the Pin Functions and Table 1.6 lists the Pin Name Information by Pin Number. Table 1.5 Pin Functions Type Power Supply Input VCC VSS Analog Power Supply AVCC, AVSS Input ...
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R8C/20 Group, R8C/21 Group Table 1.6 Pin Name Information by Pin Number Pin Control Pin Port Number 1 P3_5 2 P3_3 3 P3_4 4 MODE 5 P4_3 6 P4_4 7 RESET 8 XOUT P4_7 9 VSS/AVSS 10 XIN P4_6 11 ...
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R8C/20 Group, R8C/21 Group 2. Central Processing Unit (CPU) Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. Of these, R0, R1, R2, R3, A0, A1, and FB comprise a register bank. Two sets of register banks are ...
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R8C/20 Group, R8C/21 Group 2.1 Data Registers (R0, R1, R2 and R3 16-bit register for transfer, arithmetic, and logic operations. The same applies R3. R0 can be split into high-order bit (R0H) and low-order ...
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R8C/20 Group, R8C/21 Group 2.8.7 Interrupt Enable Flag (I) The I flag enables a maskable interrupt. An interrupt is disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The ...
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R8C/20 Group, R8C/21 Group 3. Memory 3.1 R8C/20 Group Figure 3.1 shows a Memory Map of R8C/20 Group. The R8C/20 Group has 1 Mbyte of address space from address 00000h to FFFFFh. The internal ROM is allocated lower addresses, beginning ...
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... The blank regions are reserved. Do not access locations in these regions not use addresses 20000h to 23FFFh because these areas are used for the emulator debugger. Refer to 23. Notes on Emulator Debugger. Part Number R5F21216JFP, R5F21216KFP R5F21217JFP, R5F21217KFP R5F21218JFP, R5F21218KFP R5F2121AJFP, R5F2121AKFP R5F2121CJFP, R5F2121CKFP Figure 3.2 Memory Map of R8C/21 Group Rev ...
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R8C/20 Group, R8C/21 Group 4. Special Function Registers (SFRs) An SFR (special function register control register for a peripheral function. Table 4.1 to Table 4.6 list the SFR Information. Table 4.1 SFR Information (1) Address 0000h 0001h 0002h ...
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R8C/20 Group, R8C/21 Group Table 4.2 SFR Information (2) Address 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h Timer RD0 Interrupt Control Register 0049h Timer RD1 Interrupt Control Register 004Ah Timer RE Interrupt Control Register 004Bh 004Ch 004Dh Key ...
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R8C/20 Group, R8C/21 Group Table 4.3 SFR Information (3) Address 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h 0089h 008Ah 008Bh 008Ch 008Dh 008Eh 008Fh 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009Ah 009Bh 009Ch 009Dh ...
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R8C/20 Group, R8C/21 Group Table 4.4 SFR Information (4) Address 00C0h A/D Register 00C1h 00C2h 00C3h 00C4h 00C5h 00C6h 00C7h 00C8h 00C9h 00CAh 00CBh 00CCh 00CDh 00CEh 00CFh 00D0h 00D1h 00D2h 00D3h 00D4h A/D Control Register 2 00D5h 00D6h A/D ...
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R8C/20 Group, R8C/21 Group Table 4.5 SFR Information (5) Address 0100h Timer RA Control Register 0101h Timer RA I/O Control Register 0102h Timer RA Mode Register 0103h Timer RA Prescaler Register 0104h Timer RA Register 0105h 0106h LIN Control Register ...
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R8C/20 Group, R8C/21 Group Table 4.6 SFR Information (6) Address 0140h Timer RD Control Register 0 0141h Timer RD I/O Control Register A0 0142h Timer RD I/O Control Register C0 0143h Timer RD Status Register 0 0144h Timer RD Interrupt ...
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R8C/20 Group, R8C/21 Group 5. Resets There are resets: hardware reset, power-on reset, voltage monitor 1 reset, voltage monitor 2 reset, watchdog timer reset, and software reset. Table 5.1 lists the Reset Names and Sources. Table 5.1 Reset Names and ...
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R8C/20 Group, R8C/21 Group Table 5.2 lists the Pin Functions after Reset, Figure 5.2 shows CPU Register Status after Reset, Figure 5.3 shows Reset Sequence, and Figure 5.4 shows the OFS Register. Table 5.2 Pin Functions after Reset Pin Name ...
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R8C/20 Group, R8C/21 Group fOCO-S RESET pin 10 cycles or more are needed fOCO-S clock × 32 cycles Internal reset signal Start time of flash memory (CPU clock × 14 cycles) CPU clock Address (internal address signal) NOTES: 1. Hardware ...
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R8C/20 Group, R8C/21 Group 5.1 Hardware Reset A reset is applied using the RESET pin. When an “L” signal is applied to the RESET pin while the power supply voltage meets the recommended performance condition, the pins, CPU, and SFR ...
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R8C/20 Group, R8C/21 Group VCC RESET Figure 5.5 Example of Hardware Reset Circuit and Operation RESET Figure 5.6 Example of Hardware Reset Circuit (Usage Example of External Supply Voltage Detection Circuit) and Operation Rev.2.00 Aug 27, 2008 Page 25 of ...
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R8C/20 Group, R8C/21 Group 5.2 Power-On Reset Function When the RESET pin is connected to the VCC pin via a pull-up resistor, and the VCC pin voltage level rises, the power-on reset function is enabled and the MCU resets its ...
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R8C/20 Group, R8C/21 Group 5.3 Voltage Monitor 1 Reset A reset is applied using the on-chip voltage detection 1 circuit. The voltage detection 1 circuit monitors the input voltage to the VCC pin. The voltage to monitor is Vdet1. When ...
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R8C/20 Group, R8C/21 Group 6. Voltage Detection Circuit The voltage detection circuit is a circuit to monitor the input voltage to the VCC pin. This circuit monitors the VCC input voltage by the program. And the voltage monitor 1 reset, ...
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R8C/20 Group, R8C/21 Group VCC Internal reference voltage Figure 6.1 Block Diagram of Voltage Detection Circuit Voltage detection 1 circuit VCA26 VCC + Internal - reference voltage Voltage detection 1 signal is held “H” when VCA26 bit is set to ...
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R8C/20 Group, R8C/21 Group Voltage detection 2 circuit fOCO-S VCA27 VCA13 VCC + Noise filter Internal Voltage - reference detection 2 signal voltage (Filter width: 200ns) Voltage detection 2 signal is held “H” when VCA27 bit is set to 0 ...
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R8C/20 Group, R8C/21 Group Voltage Detection Register Symbol VCA1 Bit Symbol — (b2-b0) VCA13 — (b7-b4) NOTES: 1. The VCA13 bit is enabled w ...
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R8C/20 Group, R8C/21 Group Voltage Monitor 1 Circuit Control Register Symbol VW1C Bit Symbol VW1C0 VW1C1 VW1C2 — (b3) VW1F0 VW1F1 VW1C6 VW1C7 NOTES: 1. Set the PRC3 bit in the ...
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R8C/20 Group, R8C/21 Group Voltage Monitor 2 Circuit Control Register Symbol VW2C Bit Symbol VW2C0 VW2C1 VW2C2 VW2C3 VW2F0 VW2F1 VW2C6 VW2C7 NOTES: 1. Set the PRC3 bit in the PRCR register ...
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R8C/20 Group, R8C/21 Group 6.1 VCC Input Voltage 6.1.1 Monitoring Vdet1 Vdet1 cannot be monitored. 6.1.2 Monitoring Vdet2 Set the VCA27 bit in the VCA2 register to 1 (voltage detection 2 circuit enabled). After td(E-A) has elapsed (refer to 20. ...
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R8C/20 Group, R8C/21 Group 6.2 Voltage Monitor 1 Reset Table 6.2 lists the Procedure for Setting Bits Associated with Voltage Monitor 1 Reset and Figure 6.7 shows an Example of Voltage Monitor 1 Reset Operation. To use the voltage monitor ...
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R8C/20 Group, R8C/21 Group 6.3 Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset Table 6.3 lists the Procedure for Setting Bits Associated with Voltage Monitor 2 Interrupt and Reset. Figure 6.8 shows an Example of Voltage Monitor 2 Interrupt ...
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R8C/20 Group, R8C/21 Group Vdet2 (1) 2.7 V VCA13 bit VW2C2 bit When the VW2C1 bit is set to 0 (digital filter enabled) Voltage monitor 2 interrupt request (VW2C6 = 0) Internal reset signal (VW2C6 = 1) VW2C2 bit When ...
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R8C/20 Group, R8C/21 Group 7. Programmable I/O Ports There are 41 programmable Input/Output ports (I/O ports P2, P3_0, P3_1, P3_3 to P3_5, P3_7, P4_3 to P4_5, and P6. Also, P4_6 and P4_7 can be used as input-only ports ...
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R8C/20 Group, R8C/21 Group 7.2 Effect on Peripheral Functions Programmable I/O ports function as I/O of peripheral functions (refer to Table 1.6 Pin Name Information by Pin Number). Table 7.3 lists the Setting of PDi_j Bit when Functioning as I/O ...
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R8C/20 Group, R8C/21 Group P0 Data bus P1_0 to P1_3 Output from each peripheral function Data bus Input to each peripheral function P1_4 Output from each peripheral function Data bus NOTE: 1. symbolizes a parasitic diode. Ensure the input voltage ...
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R8C/20 Group, R8C/21 Group P1_5 and P1_7 Output from each peripheral function Data bus Port latch INT1 input Input to each peripheral function P1_6 and P2 Output from each peripheral function Data bus Port latch Input to each peripheral function ...
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R8C/20 Group, R8C/21 Group P3_0 and P3_1 Output from each peripheral function Data bus P3_3 to P3_5 and P3_7 Output from each peripheral function Data bus Input to each peripheral function NOTE: 1. Ensure the input voltage on each port ...
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R8C/20 Group, R8C/21 Group P4_2/VREF P4_3 and P4_4 Data bus NOTE: 1. Ensure the input voltage on each port will not exceed VCC. Figure 7.4 Configuration of Programmable I/O Ports (4) Rev.2.00 Aug 27, 2008 Page 43 of 458 REJ09B0250-0200 ...
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R8C/20 Group, R8C/21 Group P4_5 Data bus INT0 and input to each peripheral function P4_6/XIN P4_7/XOUT NOTES: 1. Ensure the input voltage on each port will not exceed VCC. 2. When CM05 = 1, CM10 = 1, or CM13 = ...
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R8C/20 Group, R8C/21 Group P6_0 Output from each peripheral function Data bus P6_1 to P6_5 Data bus NOTE: 1. Ensure the input voltage on each port will not exceed VCC. Figure 7.6 Configuration of Programmable I/O Ports (6) Rev.2.00 Aug ...
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R8C/20 Group, R8C/21 Group P6_6 Output from each peripheral function Data bus P6_7 Data bus Input to each peripheral function NOTE: 1. Ensure the input voltage on each port will not exceed VCC. Figure 7.7 Configuration of Programmable I/O Ports ...
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R8C/20 Group, R8C/21 Group MODE MODE signal input RESET RESET signal input NOTE: 1. Ensure the input voltage on each port will not exceed VCC. Figure 7.8 Configuration of I/O Pins Rev.2.00 Aug 27, 2008 Page 47 of 458 REJ09B0250-0200 ...
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R8C/20 Group, R8C/21 Group Port Pi Direction Register ( Symbol (3) PD0 PD1 PD2 PD3 PD4 PD6 Bit Symbol PDi_0 PDi_1 PDi_2 PDi_3 PDi_4 PDi_5 PDi_6 PDi_7 ...
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R8C/20 Group, R8C/21 Group Pull-Up Control Register Symbol PUR0 Bit Symbol PU00 PU01 PU02 PU03 PU04 PU05 PU06 PU07 NOTE: 1. When this bit is set to 1 (pulled up), the ...
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R8C/20 Group, R8C/21 Group 7.4 Port Settings Table 7.4 to Table 7.47 list the port settings. Table 7.4 Port P0_0/AN7 Register PD0 Bit PD0_0 CH2 0 X Setting 1 X value NOTE: 1. Pulled ...
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R8C/20 Group, R8C/21 Group Table 7.9 Port P0_5/AN2 Register PD0 Bit PD0_5 CH2 0 X Setting 1 X value NOTE: 1. Pulled up by setting the PU01 bit in the PUR0 register to 1. ...
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R8C/20 Group, R8C/21 Group Table 7.14 Port P1_2/KI2/AN10 Register PD1 KIEN Bit PD1_2 KI2EN Setting value NOTE: 1. Pulled up by setting the PU02 bit in the PUR0 ...
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R8C/20 Group, R8C/21 Group Table 7.18 Port P1_6/CLK0 Register PD1 Bit PD1_6 SMD2 0 X Setting value NOTE: 1. Pulled up by setting the PU03 bit in the PUR0 register to ...
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R8C/20 Group, R8C/21 Group Table 7.21 Port P2_1/TRDIOB0 Register PD2 TRDOER1 Bit PD2_1 EB0 CMD1 CMD0 PWM3 Setting value ...
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R8C/20 Group, R8C/21 Group Table 7.24 Port P2_4/TRDIOA1 Register PD2 TRDOER1 Bit PD2_4 EA1 CMD1 Setting X 0 value NOTE: 1. Pulled up by setting the ...
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R8C/20 Group, R8C/21 Group Table 7.27 Port P2_7/TRDIOD1 Register PD2 TRDOER1 Bit PD2_7 ED1 CMD1 Setting 1 value ...
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R8C/20 Group, R8C/21 Group Table 7.31 Port P3_4/SDA/SCS Register PD3 SSMR2 Bit PD3_4 CSS1 Setting value NOTES: 1. Pulled up by ...
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R8C/20 Group, R8C/21 Group Table 7.35 Port P4_3 Register PD4 Bit PD4_3 0 Setting value 1 NOTE: 1. Pulled up by setting the PU10 bit in the PUR0 register to 1. Table 7.36 Port P4_4 Register PD4 Bit PD4_4 0 ...
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R8C/20 Group, R8C/21 Group Table 7.40 Port P6_0/TREO Register PD6 Bit PD6_0 0 Setting 1 value NOTE: 1. Pulled up by setting the PU14 bit in the PUR0 register to 1. Table 7.41 Port P6_1 ...
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R8C/20 Group, R8C/21 Group Table 7.46 Port P6_6/INT2/TXD1 Register PD6 PMR Bit PD6_6 U1PINSEL Setting value NOTE: 1. Pulled up by setting the PU15 ...
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R8C/20 Group, R8C/21 Group 7.5 Unassigned Pin Handling Table 7.48 lists Unassigned Pin Handling. Table 7.48 Unassigned Pin Handling Pin Name Ports P0 to P2, P3_0, P3_1, P3_3 to P3_7, P4_3 to P4_5, P6 Ports P4_6, P4_7 Port P4_2/VREF (3) ...
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R8C/20 Group, R8C/21 Group 8. Processor Mode 8.1 Processor Modes Single-chip mode can be selected as processor mode. Table 8.1 lists Features of Processor Mode. Figure 8.1 shows the PM0 Register and Figure 8.2 shows the PM1 Register. Table 8.1 ...
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R8C/20 Group, R8C/21 Group 9. Bus The bus cycles differ when accessing ROM/RAM, and when accessing SFR. Table 9.1 lists Bus Cycles by Access Space of the R8C/20 Group and Table 9.2 lists Bus Cycles by Access Space of the ...
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R8C/20 Group, R8C/21 Group 10. Clock Generation Circuit The clock generation circuit has: • XIN clock oscillation circuit • Low-speed on-chip oscillator • High-speed on-chip oscillator Table 10.1 lists Specifications of Clock Generation Circuit. Figure 10.1 shows a Clock Generation ...
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R8C/20 Group, R8C/21 Group FRA00 CM14 S Q CM10 = 1 (stop mode) R RESET Power-on reset Software reset S Q Interrupt request WAIT R instruction CM13 XIN XOUT CM13 CM05 CM02, CM05, CM06: Bits in CM0 register CM10, CM13, ...
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R8C/20 Group, R8C/21 Group System Clock Control Register Symbol CM0 Bit Symbol — (b1-b0) CM02 — (b3) — (b4) CM05 CM06 — (b7) NOTES: 1. Set ...
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R8C/20 Group, R8C/21 Group System Clock Control Register Symbol CM1 Bit Symbol CM10 — (b2-b1) CM13 CM14 CM15 CM16 CM17 NOTES: 1. Set the PRC0 bit in the PRCR ...
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R8C/20 Group, R8C/21 Group Oscillation Stop Detection Register Symbol OCD Bit Symbol OCD0 OCD1 OCD2 OCD3 — (b7-b4) NOTES: 1. Set the PRC0 bit in the PRCR register ...
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R8C/20 Group, R8C/21 Group High-Speed On-Chip Oscillator Control Register Symbol FRA0 Bit Symbol FRA00 FRA01 — (b7-b2) NOTES: Set the PRC0 bit in the PRCR ...
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R8C/20 Group, R8C/21 Group High-Speed On-Chip Oscillator Control Register Symbol FRA2 Bit Symbol FRA20 FRA21 FRA22 — (b7-b3) NOTES: Set the PRC0 bit in the PRCR ...
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R8C/20 Group, R8C/21 Group The following describes the clocks generated by the clock generation circuit. 10.1 XIN Clock This clock is supplied by a XIN clock oscillation circuit. This clock is used as the clock source for the CPU and ...
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R8C/20 Group, R8C/21 Group 10.2 On-Chip Oscillator Clocks This clock is supplied by an on-chip oscillator. The on-chip oscillator contains a high-speed on-chip oscillator and a low-speed on-chip oscillator. Either an on-chip oscillator clock is selected by the FRA01 bit ...
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R8C/20 Group, R8C/21 Group 10.3 CPU Clock and Peripheral Function Clock There are two type clocks: a CPU clock to operate the CPU and a peripheral function clock to operate the peripheral functions. Refer to Figure 10.1 Clock Generation Circuit. ...
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R8C/20 Group, R8C/21 Group 10.4 Power Control There are three power control modes. All modes other than wait and stop modes are referred to as standard operating mode. 10.4.1 Standard Operating Mode Standard operating mode is further separated into three ...
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R8C/20 Group, R8C/21 Group 10.4.1.3 Low-Speed On-Chip Oscillator Mode If the CM14 bit in the CM1 register is set to 0 (low-speed on-chip oscillator on) or the FRA01bit in the FRA0 register is set to 0, the low-speed on-chip oscillator ...
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R8C/20 Group, R8C/21 Group 10.4.2.4 Exiting Wait Mode The MCU exits wait mode by a hardware reset or peripheral function interrupt. When using a hardware reset to exit wait mode, set the ILVL2 to ILVL0 bits for the peripheral function ...
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R8C/20 Group, R8C/21 Group FMR0 Register Time until Flash Memory is Activated (T1) FMSTP Bit 0 Period of system clock (flash memory × 12 cycles + 30 µ s (max.) operates) 1 Period of system clock (flash memory × 12 ...
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R8C/20 Group, R8C/21 Group 10.4.2.5 Reducing Internal Power Consumption Internal power consumption can be reduced by using low-speed on-chip oscillator mode. Figure 10.10 shows the Procedure for Enabling Reduced Internal Power Consumption Using VCA20 bit. When enabling reduced internal power ...
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R8C/20 Group, R8C/21 Group 10.4.3 Stop Mode Since the oscillator circuits stop in wait mode, the CPU clock and peripheral function clock stop and the CPU and peripheral functions clocked by these clocks stop operating. The least power required to ...
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R8C/20 Group, R8C/21 Group FMR0 Register Time until Flash Memory is Activated (T2) FMSTP Bit 0 Period of system clock (flash memory × 12 cycles + 30 µs (max.) operates) 1 Period of system clock (flash memory × 12 cycles ...
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R8C/20 Group, R8C/21 Group Figure 10.12 shows the State Transitions in Power Control Mode. State Transition in Power Control Mode Standard operating mode High-speed clock mode CM05 = 0 CM13 = 1 OCD2 = 0 Interrupt Wait mode CPU operation ...
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R8C/20 Group, R8C/21 Group 10.5 Oscillation Stop Detection Function The oscillation stop detection function is a function to detect the stop of the XIN clock oscillating circuit. The oscillation stop detection function can be enabled and disabled by the OCD0 ...
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R8C/20 Group, R8C/21 Group Table 10.6 Determining Interrupt Source for Oscillation Stop Detection, Watchdog Timer, Voltage Monitor 1, and Voltage Monitor 2 Interrupts Generated Interrupt Source Oscillation Stop Detection ((a) or (b)) Watchdog Timer Voltage Monitor 2 No Figure 10.13 ...
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R8C/20 Group, R8C/21 Group Interrupt sources judgment NO OCD3 = 1? (XIN clock stops) YES OCD1 = 0 (Oscillation stop detection (1) interrupt disable) Jump to oscillation stop detection interrupt process routine. NOTE: 1. This disables multiple oscillation stop detection ...
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R8C/20 Group, R8C/21 Group 10.6 Notes on Clock Generation Circuit 10.6.1 Stop Mode When entering stop mode, set the FMR01 bit to “0” (CPU rewrite mode disabled) and the CM10 bit to “1” (stop mode). An instruction queue pre-reads 4 ...
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R8C/20 Group, R8C/21 Group 11. Protection Protection function protects important registers from being easily overwritten when a program runs out of control. Figure 11.1 shows the PRCR Register. The following lists the registers protected by the PRCR register. • Registers ...
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R8C/20 Group, R8C/21 Group 12. Interrupts 12.1 Interrupt Overview 12.1.1 Types of Interrupts Figure 12.1 shows the Interrupts. Software (non-maskable interrupt) Interrupt Hardware NOTES: 1. Peripheral function interrupts in the MCU are used to generate the peripheral interrupt ...
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R8C/20 Group, R8C/21 Group 12.1.2 Software Interrupts A software interrupt is generated when an instruction is executed. The software interrupts are non-maskable interrupts. 12.1.2.1 Undefined Instruction Interrupt The undefined instruction interrupt is generated when the UND instruction is executed. 12.1.2.2 ...
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R8C/20 Group, R8C/21 Group 12.1.3 Special Interrupts Special interrupts are non-maskable interrupts. 12.1.3.1 Watchdog Timer Interrupt The watchdog timer interrupt is generated by the watchdog timer. For details, refer to 13. Watchdog Timer. 12.1.3.2 Oscillation Stop Detection Interrupt Oscillation Stop ...
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R8C/20 Group, R8C/21 Group 12.1.5 Interrupts and Interrupt Vector There are 4 bytes in one vector. Set the starting address of interrupt routine in each vector table. When an interrupt request is acknowledged, the CPU branches to the address set ...
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R8C/20 Group, R8C/21 Group 12.1.5.2 Relocatable Vector Tables The relocatable vector tables occupy 256 bytes from the starting address set in the INTB register. Table 12.2 lists the Relocatable Vector Tables. Table 12.2 Relocatable Vector Tables Vector Address Interrupt Source ...
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R8C/20 Group, R8C/21 Group 12.1.6 Interrupt Control The following describes enable/disable the maskable interrupts and set the priority order to acknowledge. The contents explained does not apply to the nonmaskable interrupts. Use the I flag in the FLG register, IPL ...
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R8C/20 Group, R8C/21 Group (1) Interrupt Control Register Symbol TRD0IC TRD1IC SSUIC/IICIC Bit Symbol ILVL0 ILVL1 ILVL2 IR — (b7-b4) NOTES rew rite the interrupt control register, rew rite it ...
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R8C/20 Group, R8C/21 Group INTi Interrupt Control Register ( Symbol INT2IC INT1IC INT3IC INT0IC Bit Symbol ILVL0 ILVL1 ILVL2 IR POL — (b5) — (b7-b6) NOTES: 1. ...
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R8C/20 Group, R8C/21 Group 12.1.6.1 I Flag The I flag enables or disables the maskable interrupt. Setting the I flag to 1 (enabled) enables the maskable interrupt. Setting the I flag to 0 (disabled) disables all maskable interrupts. 12.1.6.2 IR ...
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R8C/20 Group, R8C/21 Group 12.1.6.4 Interrupt Sequence An interrupt sequence is performed between an interrupt request acknowledgement and interrupt routine execution. When an interrupt request is generated while an instruction is executed, the CPU determines its interrupt priority level after ...
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R8C/20 Group, R8C/21 Group 12.1.6.5 Interrupt Response Time Figure 12.7 shows an Interrupt Response Time. The interrupt response time is the period between an interrupt request generation and the execution of the first instruction in an interrupt routine. An interrupt ...
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R8C/20 Group, R8C/21 Group 12.1.6.7 Saving a Register In the interrupt sequence, the FLG register and PC are saved to the stack. After 4 high-order bits in the PC and 4 high-order (IPL) and 8 low-order bits in the FLG ...
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R8C/20 Group, R8C/21 Group 12.1.6.8 Returning from an Interrupt Routine When the REIT instruction is executed at the end of an interrupt routine, the FLG register and PC, which have been saved to the stack, are automatically returned. The program, ...
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R8C/20 Group, R8C/21 Group 12.1.6.10 Interrupt Priority Judgement Circuit The interrupt priority judgement circuit selects the highest priority interrupt. Figure 12.11 shows the Interrupt Priority Level Judgement Circuit. Priority level of each interrupt INT3 Timer RB Timer RA INT0 INT1 ...
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R8C/20 Group, R8C/21 Group 12.2 INT Interrupt 12.2.1 INTi Interrupt ( The INTi interrupt is generated by an INTi input. When using the INTi interrupt, the INTiEN bit in the INTEN register is set to 1 ...
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R8C/20 Group, R8C/21 Group _____ INT Input Filter Select Register Symbol INTF Bit Symbol INT0F0 INT0F1 INT1F0 INT1F1 INT2F0 INT2F1 INT3F0 INT3F1 Figure 12.13 INTF Register Rev.2.00 Aug 27, 2008 Page 102 ...
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R8C/20 Group, R8C/21 Group 12.2.2 INTi Input Filter ( The INTi input contains a digital filter. The sampling clock is selected by the INTiF1 to INTiF0 bits in the INTF register. The IR bit in the ...
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R8C/20 Group, R8C/21 Group 12.3 Key Input Interrupt A key input interrupt request is generated by one of the input edges of the K10 to K13 pins. The key input interrupt can be used as a key-on wake-up function to ...
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R8C/20 Group, R8C/21 Group (1) Key Input Enable Register Symbol KIEN Bit Symbol KI0EN KI0PL KI1EN KI1PL KI2EN KI2PL KI3EN KI3PL NOTE: 1. The IR bit in the KUPIC register may be ...
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R8C/20 Group, R8C/21 Group 12.4 Address Match Interrupt An address match interrupt request is generated immediately before executing the instruction at the address indicated by the RMADi register ( 1). This interrupt is used for a break ...
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R8C/20 Group, R8C/21 Group Address Match Interrupt Enable Register Symbol AIER Bit Symbol AIER0 AIER1 — (b7-b2) Address Match Interrupt Register (b23) (b19) (b16) (b15) b7 ...
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R8C/20 Group, R8C/21 Group 12.5 Timer RD Interrupt, Clock Synchronous Serial I/O with Chip Select Interrupts 2 and I C bus Interface Interrupts (Interrupts with Multiple Interrupt Request Sources) Timer RD (channel 0), timer RD (channel 1), clock synchronous serial ...
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R8C/20 Group, R8C/21 Group Controlling an interrupt with the I flag, IR bit, ILVL0 to ILVL2 bits and IPL by Timer RD (channel 0), Timer RD (channel 1), clock synchronous serial I/O with chip select and I maskable interrupts. However, ...
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R8C/20 Group, R8C/21 Group 12.6 Notes on Interrupts 12.6.1 Reading Address 00000h Do not read the address 00000h by a program. When a maskable interrupt request is acknowledged, the CPU reads interrupt information (interrupt number and interrupt request level) from ...
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R8C/20 Group, R8C/21 Group 12.6.4 Changing Interrupt Sources The IR bit in the interrupt control register may be set to 1 (interrupt requested) when the interrupt source changes. When using an interrupt, set the IR bit to 0 (no interrupt ...
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R8C/20 Group, R8C/21 Group 12.6.5 Changing Interrupt Control Register Contents (a) Each interrupt control register can only be changed while interrupt requests corresponding to that register are not generated. If interrupt requests may be generated, disable the interrupts before changing ...
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R8C/20 Group, R8C/21 Group 13. Watchdog Timer The watchdog timer is a function to detect when the program is out of control. To use the watchdog timer is recommend for improving reliability of a system. The watchdog timer contains a ...
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R8C/20 Group, R8C/21 Group Option Function Select Register Symbol OFS Bit Symbol WDTON — (b1) ROMCR ROMCP1 — (b5-b4) LVD1ON CSPROINI NOTES: 1. The OFS register is on the ...
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R8C/20 Group, R8C/21 Group Watchdog Timer Reset Register b7 b0 Symbol WDTR When w riting 00h before w riting FFh, the w atchdog timer is reset. The default value of the w atchdog timer is set to 7FFFh w hen ...
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R8C/20 Group, R8C/21 Group 13.1 Count Source Protection Mode Disabled The count source of the watchdog timer is the CPU clock when count source protection mode is disabled. Table 13.2 lists the Watchdog Timer Specifications (with Count Source Protection Mode ...
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R8C/20 Group, R8C/21 Group 13.2 Count Source Protection Mode Enabled The count source of the watchdog timer is the low-speed on-chip oscillator clock when count source protection mode is enabled. If the CPU clock stops when the program is out ...
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R8C/20 Group, R8C/21 Group 14. Timers The MCU contains two 8-bit timers with 8-bit prescaler, two 16-bit timers, and a timer with a 4-bit counter, and an 8- bit counter. The two 8-bit timers with the 8-bit prescaler contain timer ...
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R8C/20 Group, R8C/21 Group Table 14.1 Functional Comparison of Timers Item Configuration Count Count Sources Function Timer mode Pulse output mode Event counter mode Pulse width measurement mode Pulse period measurement mode Programmable waveform generation mode Programmable one- shot generation ...
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R8C/20 Group, R8C/21 Group 14.1 Timer RA Timer 8-bit timer with an 8-bit prescaler. The prescaler and timer consist of the reload register and counter. The reload register and counter are allocated at the same address. When ...
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R8C/20 Group, R8C/21 Group (4) Timer RA Control Register Symbol TRACR Bit Symbol TSTART TCSTF TSTOP — (b3) TEDGF TUNDF — (b7-b6) NOTES: 1. Refer to 14.1.6 Notes on Tim er RA. ...
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R8C/20 Group, R8C/21 Group (1) Timer RA Mode Register Symbol TRAMR Bit Symbol TMOD0 TMOD1 TMOD2 — (b3) TCK0 TCK1 TCK2 TCKCUT NOTE: 1. When both the TSTART and TCSTF bits in ...
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R8C/20 Group, R8C/21 Group Timer RA Register b7 b0 Symbol Mode All Modes NOTE: 1. When the TSTOP bit in the TRACR register is set to 1, the TRA register is set to FFh. Figure 14.4 TRA Register Rev.2.00 Aug ...
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R8C/20 Group, R8C/21 Group 14.1.1 Timer Mode In this mode, the timer counts an internally generated count source (see Table 14.2 Timer Mode Specifications). Figure 14.5 shows the TRAIOC Register in Timer Mode. Table 14.2 Timer Mode Specifications Item Count ...
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R8C/20 Group, R8C/21 Group 14.1.1.1 Timer Write Control during Count Operation Timer RA has a prescaler and a timer (which counts the prescaler underflows). The prescaler and timer each consist of a reload register and a counter. When writing to ...
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R8C/20 Group, R8C/21 Group 14.1.2 Pulse Output Mode Pulse output mode is mode to count the count source internally generated and outputs the pulse which inverts the polarity from the TRAIO pin each time the timer underflows (see Table 14.3 ...
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R8C/20 Group, R8C/21 Group Timer RA I/O Control Register Symbol TRAIOC Bit Symbol TEDGSEL TOPCR TOENA TIOSEL TIPF0 TIPF1 — (b7-b6) Figure 14.7 TRAIOC Register in Pulse Output Mode Rev.2.00 ...
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R8C/20 Group, R8C/21 Group 14.1.3 Event Counter Mode Event counter mode is mode to count an external signal which inputs from the INT1/TRAIO pin (see Table 14.4 Event Counter Mode Specifications). Figure 14.8 shows the TRAIOC Register in Event Counter ...
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R8C/20 Group, R8C/21 Group Timer RA I/O Control Register Symbol TRAIOC Bit Symbol TEDGSEL TOPCR TOENA TIOSEL TIPF0 TIPF1 — (b7-b6) NOTE: 1. When the same value from the TRAIO pin ...
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R8C/20 Group, R8C/21 Group 14.1.4 Pulse Width Measurement Mode Pulse width measurement mode is mode to measure the pulse width of an external signal which inputs from the INT1/TRAIO pin (see Table 14.5 Pulse Width Measurement Mode Specifications). Figure 14.9 ...
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R8C/20 Group, R8C/21 Group Timer RA I/O Control Register Symbol TRAIOC Bit Symbol TEDGSEL TOPCR TOENA TIOSEL TIPF0 TIPF1 — (b7-b6) NOTE: 1. When the same value from the TRAIO ...
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R8C/20 Group, R8C/21 Group n = high-level: the contents of TRA register, low-level: the contents of TRAPRE register FFFFh n 0000h Set program 1 TSTART bit in TRACR register 0 1 Measurement pulse (TRAIO pin input) 0 ...
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R8C/20 Group, R8C/21 Group 14.1.5 Pulse Period Measurement Mode Pulse period measurement mode is mode to measure the pulse period of an external signal which inputs from the INT1/TRAIO pin (see Table 14.6 Pulse Period Measurement Mode Specifications). Figure 14.11 ...
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R8C/20 Group, R8C/21 Group Timer RA I/O Control Register Symbol TRAIOC Bit Symbol TEDGSEL TOPCR TOENA TIOSEL TIPF0 TIPF1 — (b7-b6) NOTE: 1. When the same value from the TRAIO ...
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R8C/20 Group, R8C/21 Group Underflow signal of timer RA prescaler Set program 1 TSTART bit in TRACR register 0 Starts counting 1 Measurement pulse (TRAIO pin input) 0 Contents of TRA Contents of read-out (1) buffer 1 ...
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R8C/20 Group, R8C/21 Group 14.1.6 Notes on Timer RA • Timer RA stops counting after reset. Set the value to timer RA and timer RA prescaler before the count starts. • Even if the prescaler and timer RA is read ...
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R8C/20 Group, R8C/21 Group 14.2 Timer RB Timer 8-bit timer with an 8-bit prescaler. The prescaler and timer consist of the reload register and counter. (Refer to Table 14.7 to 14.10 the Specification of Each Modes). Timer ...
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R8C/20 Group, R8C/21 Group Timer RB Control Register Symbol TRBCR Bit Symbol TSTART TCSTF TSTOP — (b7-b3) NOTES: 1. Refer to 14.2.5 Notes on Tim When the TSTOP ...
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R8C/20 Group, R8C/21 Group Timer RB I/O Control Register Symbol TRBIOC Bit Symbol TOPL TOCNT INOSTG INOSEG — (b7-b4) Timer RB Mode Register Symbol ...
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R8C/20 Group, R8C/21 Group Timer RB Prescaler Register b7 b0 Timer mode Programmable w aveform generation mode Programmable one-shot generation mode Programmable w ait one-shot generation mode NOTE: 1. When the TSTOP bit in the TRBCR register is set to ...
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R8C/20 Group, R8C/21 Group 14.2.1 Timer Mode Timer mode is mode to count a count source which is internally generated or timer RA underflow (see Table 14.7 Timer Mode Specifications). The TRBOCR and TRBSC registers are unused in timer mode. ...
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R8C/20 Group, R8C/21 Group 14.2.1.1 Timer Write Control during Count Operation Timer RB has a prescaler and a timer (which counts the prescaler underflows). The prescaler and timer each consist of a reload register and a counter. In timer mode, ...
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R8C/20 Group, R8C/21 Group When the TWRC bit is set to 0 (write to reload register and counter) Set 01h to the TRBPRE register and 25h to the TRBPR register by a program. Count source Reloads register of Previous value ...
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R8C/20 Group, R8C/21 Group 14.2.2 Programmable Waveform Generation Mode Programmable waveform generation mode is mode to invert the signal output from the TRBO pin each time the counter underflows, while the values in the TRBPR and TRBSC registers are counted ...
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R8C/20 Group, R8C/21 Group Timer RB I/O Control Register Symbol TRBIOC Bit Symbol TOPL TOCNT INOSTG INOSEG — (b7-b4) Figure 14.19 TRBIOC Register in Programmable Waveform Generation Mode Rev.2.00 Aug ...
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R8C/20 Group, R8C/21 Group 1 TSTART bit in TRBCR register 0 Count source Timer RB prescaler underflow signal Counter of timer bit in TRBIC register 0 1 TOPL bit in TRBIO register 0 1 TRBO pin output ...
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R8C/20 Group, R8C/21 Group 14.2.3 Programmable One-shot Generation Mode Programmable one-shot generation mode is mode to output the one-shot pulse from the TRBO pin by a program or an external trigger input (input to the INT0 pin) (see Table 14.9 ...
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R8C/20 Group, R8C/21 Group Timer RB I/O Control Register Symbol TRBIOC Bit Symbol TOPL TOCNT INOSTG INOSEG — (b7-b4) NOTE: 1. Refer to 14.2.3.1 One-shot Trigger Selection . Figure 14.21 TRBIOC ...
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R8C/20 Group, R8C/21 Group 1 TSTART bit in TRBCR register 0 Set program 1 TOSSTF bit in TRBOCR register 0 INT0 pin input Count source Timer RB prescaler underflow signal Counter of timer bit ...
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R8C/20 Group, R8C/21 Group 14.2.3.1 One-Shot Trigger Selection In programmable one-shot generation mode and programmable wait one-shot generation mode, operation starts when a one-shot trigger is generated while the TCSTF bit in the TRBCR register is set to 1 (count ...
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R8C/20 Group, R8C/21 Group 14.2.4 Programmable Wait One-shot Generation Mode Programmable wait one-shot generation mode is mode to output the one-shot pulse from the TRBO pin by a program or an external trigger input (input to the INT0 pin) (see ...
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R8C/20 Group, R8C/21 Group Table 14.10 Programmable Wait One-Shot Generation Mode Specifications Item Count Sources Count Operations Wait Time One-Shot Pulse Output Time (n+1)(p+1)/fi Count Start Conditions Count Stop Conditions Interrupt Request Generation Timing TRBO Pin Function INT0 Pin Functions ...
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R8C/20 Group, R8C/21 Group Timer RB I/O Control Register Symbol TRBIOC Bit Symbol TOPL TOCNT INOSTG INOSEG — (b7-b4) NOTE: 1. Refer to 14.2.3.1 One-shot Trigger Selection. Figure 14.23 TRBIOC Register ...
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R8C/20 Group, R8C/21 Group 1 TSTART bit in TRBCR register 0 1 TOSSTF bit in TRBOCR register 0 INT0 pin input Count source Timer RB prescaler underflow signal Counter of timer bit in TRBIC register 0 1 ...
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R8C/20 Group, R8C/21 Group 14.2.5 Notes on Timer RB • Timer RB stops counting after reset. Set the value to timer RB and timer RB prescaler before the count starts. • Even if the prescaler and timer RB is read ...
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R8C/20 Group, R8C/21 Group 14.2.5.2 Programmable waveform generation mode The following three workarounds should be performed in programmable waveform generation mode. (1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the ...
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R8C/20 Group, R8C/21 Group • Workaround example (b): As shown in Figure 14.26 detect the start of the primary period by the TRBO pin output level and write to registers TRBSC and TRBPR. These write operations must be completed by ...
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R8C/20 Group, R8C/21 Group 14.2.5.4 Programmable wait one-shot generation mode The following three workarounds should be performed in programmable wait one-shot generation mode. (1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), ...
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R8C/20 Group, R8C/21 Group 14.3 Timer RD Timer RD has 2 16-bit timers (channels 0 and 1). Each channel has 4 I/O pins. The operation clock of Timer fOCO40M. Table 14.11 lists the Timer RD Operation ...
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R8C/20 Group, R8C/21 Group Table 14.12 Pin Functions TRDIOA0/TRDCLK(P2_0) Register TRDOER1 TRDFCR Bit EA0 PWM3 STCLK CMD1, CMD0 IOA3 IOA2_IOA0 Setting 1 0 value Other than above X: can be 0 ...
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R8C/20 Group, R8C/21 Group Table 14.15 Pin Functions TRDIOD0(P2_3) Register TRDOER1 TRDFCR Bit ED0 PWM3 CMD1, CMD0 Setting value Other than above X: can change ...
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R8C/20 Group, R8C/21 Group Table 14.18 Pin Functions TRDIOC1(P2_6) Register TRDOER1 TRDFCR Bit EC1 PWM3 CMD1, CMD0 Setting value Other than above X: can change ...
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R8C/20 Group, R8C/21 Group Channel i TRDi register TRDGRAi register TRDGRBi register TRDGRCi register TRDGRDi register TRDDFi register TRDCRi register TRDIORAi register TRDIORCi register TRDSRi register TRDIERi register TRDPOCRi register TRDSTR register TRDMR register TRDPMR register TRDFCR register TRDOER1 register ...
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R8C/20 Group, R8C/21 Group 14.3.1 Count Source The count source selection can be used in all modes. However, in PWM3 mode, the external clock cannot be selected. Table 14.21 Count Source Selection Count Source f1, f2, f4, f8, f32 The ...
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R8C/20 Group, R8C/21 Group 14.3.2 Buffer Operation The TRDGRCi register can be used as the buffer register of the TRDGRAi register, and the TRDGRDi register can be used as the buffer register of the TRDGRBi register by the BFCi and ...
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R8C/20 Group, R8C/21 Group TRDGRCi register (buffer) TRDi register TRDGRAi register TRDGRCi register (buffer) TRDIOAi output The above applies to the following conditions: • BFCi bit in the TRDMR register is set to 1. (The ...
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R8C/20 Group, R8C/21 Group 14.3.3 Synchronous Operation The TRD1 register is synchronized with the TRD0 register. • Synchronous preset When the SYNC bit in the TRDMR register is set to 1 (synchronous operation), the data is written to both the ...
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R8C/20 Group, R8C/21 Group 14.3.4 Pulse Output Forced Cutoff In the output compare function, PWM mode, reset synchronous PWM mode, complementary PWM mode and PWM3 mode, the TRDIOji output pin can be forcibly set to the programmable I/O port by ...
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R8C/20 Group, R8C/21 Group INT0 input PTO bit Figure 14.32 Pulse Output Forced Cutoff Rev.2.00 Aug 27, 2008 Page 169 of 458 REJ09B0250-0200 EA0 bit EA0 bit writing D Q value S output data output data EB0 bit EB0 bit ...
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R8C/20 Group, R8C/21 Group 14.3.5 Input Capture Function The input capture function is to measure the external signal width and period. The content in the TRDi register (counter) is transferred to the TRDGRji register as a trigger of the TRDIOji ...
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R8C/20 Group, R8C/21 Group Table 14.23 Input Capture Function Specifications Item Count Sources Count Operations Count Period Count Start Condition Count Stop Condition Interrupt Request Generation Timing TRDIOA0 Pin Function TRDIOB0, TRDIOC0, TRDIOD0, TRDIOA1 to TRDIOD1 Pin Functions INT0 Pin ...
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R8C/20 Group, R8C/21 Group (1) Timer RD Start Register Symbol TRDSTR Bit Symbol TSTART0 TSTART1 CSEL0 CSEL1 — (b7 - b4) NOTE: 1. Set the TRDSTR register using the MOV ...
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R8C/20 Group, R8C/21 Group Timer RD PWM Mode Register Symbol TRDPMR Bit Symbol PWMB0 PWMC0 PWMD0 — (b3) PWMB1 PWMC1 PWMD1 — (b7) Figure 14.35 TRDPMR ...
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R8C/20 Group, R8C/21 Group Timer RD Function Control Register Symbol TRDFCR Bit Symbol CMD0 CMD1 OLS0 OLS1 ADTRG ADEG STCLK PWM3 NOTES: 1. Set bits CMD1 to CMD0 w ...
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R8C/20 Group, R8C/21 Group Timer RD Digital Filter Function Selection Register Symbol TRDDF0 TRDDF1 Bit Symbol DFA DFB DFC DFD — (b5 - b4) DFCK0 DFCK1 ...
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R8C/20 Group, R8C/21 Group Timer RD Control Register Symbol TRDCR0 TRDCR1 Bit Symbol TCK0 TCK1 TCK2 CKEG0 CKEG1 CCLR0 CCLR1 CCLR2 NOTES: 1. This bit is ...
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R8C/20 Group, R8C/21 Group Timer RD I/O Control Register Symbol TRDIORA0 TRDIORA1 Bit Symbol IOA0 IOA1 IOA2 IOA3 IOB0 IOB1 IOB2 — (b7) NOTES: ...
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R8C/20 Group, R8C/21 Group Timer RD I/O Control Register Symbol TRDIORC0 TRDIORC1 Bit Symbol IOC0 IOC1 IOC2 IOC3 IOD0 IOD1 IOD2 IOD3 ...
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R8C/20 Group, R8C/21 Group Timer RD Status Register Symbol TRDSR0 TRDSR1 Bit Symbol IMFA IMFB IMFC IMFD OVF UDF — (b7 - b6) NOTES: 1. Nothing ...
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R8C/20 Group, R8C/21 Group Timer RD Interrupt Enable Register Symbol TRDIER0 TRDIER1 Bit Symbol IMIEA IMIEB IMIEC IMIED OVIE — (b7 - b5) Figure 14.42 Registers ...
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R8C/20 Group, R8C/21 Group Timer RD General Register Ai, Bi, Ci and (b15) (b8 Refer to Table 14.24 TRDGRji Register Functions in Input Capture Function NOTE: 1. Access the TRDGRAi to ...
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R8C/20 Group, R8C/21 Group TRDCLK input count source Count value in TRDi register FFFFh 0009h 0006h 0000h 1 TSTARTi bit in TRDSTR register 0 TRDIOAi input TRDGRAi register TRDGRCi register 1 IMFA bit in TRDSRi register 0 1 OVF bit ...