IC R8C/2B MCU FLASH 96+2K 64LQFP

R5F212BASNFA#U0

Manufacturer Part NumberR5F212BASNFA#U0
DescriptionIC R8C/2B MCU FLASH 96+2K 64LQFP
ManufacturerRenesas Electronics America
SeriesR8C/2x/2B
R5F212BASNFA#U0 datasheet
 


Specifications of R5F212BASNFA#U0

Core ProcessorR8CCore Size16/32-Bit
Speed20MHzConnectivityI²C, LIN, SIO, SSU, UART/USART
PeripheralsPOR, PWM, Voltage Detect, WDTNumber Of I /o55
Program Memory Size96KB (96K x 8)Program Memory TypeFLASH
Ram Size7K x 8Voltage - Supply (vcc/vdd)2.2 V ~ 5.5 V
Data ConvertersA/D 12x10b; D/A 2x8bOscillator TypeInternal
Operating Temperature-20°C ~ 85°CPackage / Case64-LQFP
For Use WithR0K5212D8S001BE - KIT STARTER FOR R8C/2DR0K5212D8S000BE - KIT DEV FOR R8C/2DLead Free Status / RoHS StatusLead free / RoHS Compliant
Eeprom Size-  
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R8C/2A Group, R8C/2B Group
2.1
Data Registers (R0, R1, R2, and R3)
R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3. R0 can be split
into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers. R1H and R1L are
analogous to R0H and R0L. R2 can be combined with R0 and used as a 32-bit data register (R2R0). R3R1 is
analogous to R2R0.
2.2
Address Registers (A0 and A1)
A0 is a 16-bit register for address register indirect addressing and address register relative addressing. It is also
used for transfer, arithmetic, and logic operations. A1 is analogous to A0. A1 can be combined with A0 and as a 32-
bit address register (A1A0).
2.3
Frame Base Register (FB)
FB is a 16-bit register for FB relative addressing.
2.4
Interrupt Table Register (INTB)
INTB is a 20-bit register that indicates the start address of an interrupt vector table.
2.5
Program Counter (PC)
PC is 20 bits wide and indicates the address of the next instruction to be executed.
2.6
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointers (SP), USP, and ISP, are each 16 bits wide. The U flag of FLG is used to switch between
USP and ISP.
2.7
Static Base Register (SB)
SB is a 16-bit register for SB relative addressing.
2.8
Flag Register (FLG)
FLG is an 11-bit register indicating the CPU state.
2.8.1
Carry Flag (C)
The C flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit.
2.8.2
Debug Flag (D)
The D flag is for debugging only. Set it to 0.
2.8.3
Zero Flag (Z)
The Z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0.
2.8.4
Sign Flag (S)
The S flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0.
2.8.5
Register Bank Select Flag (B)
Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is set to 1.
2.8.6
Overflow Flag (O)
The O flag is set to 1 when an operation results in an overflow; otherwise to 0.
Rev.2.10
Nov 26, 2007
Page 18 of 60
REJ03B0182-0210
2. Central Processing Unit (CPU)