IC R8C/2B MCU FLASH 96+2K 64LQFP

R5F212BASNFA#U0

Manufacturer Part NumberR5F212BASNFA#U0
DescriptionIC R8C/2B MCU FLASH 96+2K 64LQFP
ManufacturerRenesas Electronics America
SeriesR8C/2x/2B
R5F212BASNFA#U0 datasheet
 


Specifications of R5F212BASNFA#U0

Core ProcessorR8CCore Size16/32-Bit
Speed20MHzConnectivityI²C, LIN, SIO, SSU, UART/USART
PeripheralsPOR, PWM, Voltage Detect, WDTNumber Of I /o55
Program Memory Size96KB (96K x 8)Program Memory TypeFLASH
Ram Size7K x 8Voltage - Supply (vcc/vdd)2.2 V ~ 5.5 V
Data ConvertersA/D 12x10b; D/A 2x8bOscillator TypeInternal
Operating Temperature-20°C ~ 85°CPackage / Case64-LQFP
For Use WithR0K5212D8S001BE - KIT STARTER FOR R8C/2DR0K5212D8S000BE - KIT DEV FOR R8C/2DLead Free Status / RoHS StatusLead free / RoHS Compliant
Eeprom Size-  
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Page 21
22
Page 22
23
Page 23
24
Page 24
25
Page 25
26
Page 26
27
Page 27
28
Page 28
29
Page 29
30
Page 30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
Page 21/66

Download datasheet (572Kb)Embed
PrevNext
R8C/2A Group, R8C/2B Group
2.8.7
Interrupt Enable Flag (I)
The I flag enables maskable interrupts.
Interrupt are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0
when an interrupt request is acknowledged.
2.8.8
Stack Pointer Select Flag (U)
ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1.
The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software
interrupt numbers 0 to 31 is executed.
2.8.9
Processor Interrupt Priority Level (IPL)
IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has higher priority than IPL, the interrupt is enabled.
2.8.10
Reserved Bit
If necessary, set to 0. When read, the content is undefined.
Rev.2.10
Nov 26, 2007
Page 19 of 60
REJ03B0182-0210
2. Central Processing Unit (CPU)