C8051F018-GQR Silicon Laboratories Inc, C8051F018-GQR Datasheet - Page 135

• Manufacturer Part Number: C8051F018-GQR
• Description: IC 8051 MCU 16K FLASH 64TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F018r

Specifications of C8051F018-GQR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 2.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Processor Series: C8051F0x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 1.25 KB
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4 bit
• Operating Supply Voltage: 2.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F005DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

17.3.
Timer 3 is a 16-bit timer formed by the two 8-bit SFRs, TMR3L (low byte) and TMR3H (high byte). The input for
Timer 3 is the system clock (divided by either one or twelve as specified by the Timer 3 Clock Select bit T3M in the
Timer 3 Control Register TMR3CN). Timer 3 is always configured as an auto-reload timer, with the reload value
held in the TMR3RLL (low byte) and TMR3RLH (high byte) registers. Timer 3 can be used to start an ADC Data
Conversion, for SMBus timing (see Section 14.5), or as a general-purpose timer. Timer 3 does not have a counter
mode.
135
SYSCLK
Bit7:
Bits6-3: UNUSED. Read = 0000b, Write = don’t care.
Bit2:
Bit1:
Bit0:
C8051F018
C8051F019
R/W
TF3
Bit7
Timer 3
Set by hardware when Timer 3 overflows from 0xFFFF to 0x0000. When the Timer 3
interrupt is enabled, setting this bit causes the CPU to vector to the Timer 3 Interrupt
service routine. This bit is not automatically cleared by hardware and must be cleared by
software.
TR3: Timer 3 Run Control.
This bit enables/disables Timer 3.
0: Timer 3 disabled.
1: Timer 3 enabled.
T3M: Timer 3 Clock Select.
This bit controls the division of the system clock supplied to Counter/Timer 3.
0: Counter/Timer 3 uses the system clock divided by 12.
1: Counter/Timer 3 uses the system clock.
UNUSED. Read = 0, Write = don’t care.
TF3: Timer3 Overflow Flag.
(from SMBus)
SCL
R/W
Bit6
-
12
Crossbar
TOE
0
1
TR3
Figure 17.20. TMR3CN: Timer 3 Control Register
R/W
Bit5
-
T3M
Figure 17.19. Timer 3 Block Diagram
R/W
Bit4
-
Reload
TCLK
Rev. 1.2
R/W
Bit3
TMR3RLL TMR3RLH
-
TMR3L
TMR3H
TR3
R/W
Bit2
T3M
R/W
Bit1
T3M
TF3
TR3
(to ADC)
R/W
Bit0
-
Interrupt
SFR Address:
Reset Value
00000000
0x91