C8051F018-GQR Silicon Laboratories Inc, C8051F018-GQR Datasheet - Page 4

• Manufacturer Part Number: C8051F018-GQR
• Description: IC 8051 MCU 16K FLASH 64TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F018r

Specifications of C8051F018-GQR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 2.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Processor Series: C8051F0x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 1.25 KB
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4 bit
• Operating Supply Voltage: 2.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F005DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

12. OSCILLATOR .................................................................................................................... 81
13. PORT INPUT/OUTPUT..................................................................................................... 85
14. SMBus / I2C Bus.................................................................................................................. 96
15. SERIAL PERIPHERAL INTERFACE BUS.................................................................. 106
Figure 11.3. WDTCN: Watchdog Timer Control Register ...............................................................................78
Figure 11.4. RSTSRC: Reset Source Register...................................................................................................79
Table 11.1. Reset Electrical Characteristics ......................................................................................................80
Figure 12.1. Oscillator Diagram ........................................................................................................................81
Figure 12.2. OSCICN: Internal Oscillator Control Register .............................................................................82
Table 12.1. Internal Oscillator Electrical Characteristics ..................................................................................82
Figure 12.3. OSCXCN: External Oscillator Control Register...........................................................................83
12.1. External Crystal Example ........................................................................................................................84
12.2. External RC Example ..............................................................................................................................84
12.3. External Capacitor Example ....................................................................................................................84
13.1. Priority Cross Bar Decoder......................................................................................................................85
13.2. Port I/O Initialization...............................................................................................................................85
Figure 13.1. Port I/O Functional Block Diagram ..............................................................................................86
Figure 13.2. Port I/O Cell Block Diagram.........................................................................................................87
Table 13.1. Crossbar Priority Decode ...............................................................................................................85
Figure 13.3. XBR0: Port I/O CrossBar Register 0 ............................................................................................89
Figure 13.4. XBR1: Port I/O CrossBar Register 1 ............................................................................................90
Figure 13.5. XBR2: Port I/O CrossBar Register 2 ............................................................................................91
13.3. General Purpose Port I/O.........................................................................................................................92
13.4. Configuring Ports Which are not Pinned Out..........................................................................................92
Figure 13.6. P0: Port0 Register .........................................................................................................................92
Figure 13.7. PRT0CF: Port0 Configuration Register ........................................................................................92
Figure 13.8. P1: Port1 Register .........................................................................................................................93
Figure 13.9. PRT1CF: Port1 Configuration Register ........................................................................................93
Figure 13.10. PRT1IF: Port1 Interrupt Flag Register........................................................................................93
Figure 13.11. P2: Port2 Register .......................................................................................................................94
Figure 13.12. PRT2CF: Port2 Configuration Register ......................................................................................94
Figure 13.13. P3: Port3 Register .......................................................................................................................95
Figure 13.14. PRT3CF: Port3 Configuration Register ......................................................................................95
Table 13.2. Port I/O DC Electrical Characteristics............................................................................................95
Figure 14.1. SMBus Block Diagram .................................................................................................................96
Figure 14.2. Typical SMBus Configuration ......................................................................................................97
14.1. Supporting Documents ............................................................................................................................97
14.2. Operation .................................................................................................................................................98
Figure 14.3. SMBus Transaction.......................................................................................................................98
14.3. Arbitration ...............................................................................................................................................99
14.4. Clock Low Extension ..............................................................................................................................99
14.5. Timeouts ..................................................................................................................................................99
14.6. SMBus Special Function Registers..........................................................................................................99
Figure 14.4. SMB0CN: SMBus Control Register ............................................................................................101
Figure 14.5. SMB0CR: SMBus Clock Rate Register ......................................................................................102
Figure 14.6. SMB0DAT: SMBus Data Register .............................................................................................103
Figure 14.7. SMB0ADR: SMBus Address Register .......................................................................................103
Figure 14.8. SMB0STA: SMBus Status Register............................................................................................104
Table 14.1. SMBus Status Codes ....................................................................................................................105
Figure 15.1. SPI Block Diagram .....................................................................................................................106
Figure 15.2. Typical SPI Interconnection........................................................................................................107
15.1. Signal Descriptions................................................................................................................................107
15.2. Operation ...............................................................................................................................................108
Figure 15.3. Full Duplex Operation.................................................................................................................108
Rev. 1.2
C8051F018
C8051F019
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