MC68HC11E0CFNE2R Freescale Semiconductor, MC68HC11E0CFNE2R Datasheet - Page 132

IC MCU 8BIT 2MHZ 52-PLCC

MC68HC11E0CFNE2R

Manufacturer Part Number
MC68HC11E0CFNE2R
Description
IC MCU 8BIT 2MHZ 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheet

Specifications of MC68HC11E0CFNE2R

Core Processor
HC11
Core Size
8-Bit
Speed
2MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Type
ROMless
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Processor Series
HC11E
Core
HC11
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI, SPI
Maximum Clock Frequency
2 MHz
Number Of Programmable I/os
38
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68HC11E0CFNE2R
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Timing Systems
input capture register pair inhibits a new capture transfer for one bus cycle. If a double-byte read
instruction, such as load double accumulator D (LDD), is used to read the captured value, coherency is
assured. When a new input capture occurs immediately after a high-order byte read, transfer is delayed
for an additional cycle but the value is not lost.
132
Register name: Timer Input Capture 1 Register (High)
Register name: Timer Input Capture 1 Register (Low)
Register name: Timer Input Capture 2 Register (High)
Register name: Timer Input Capture 2 Register (Low)
Register name: Timer Input Capture 3 Register (High)
Register name: Timer Input Capture 3 Register (Low)
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
Write:
Bit 15
Bit 15
Bit 15
Figure 9-4. Timer Input Capture 1 Register Pair (TIC1)
Figure 9-5. Timer Input Capture 2 Register Pair (TIC2)
Figure 9-6. Timer Input Capture 3 Register Pair (TIC3)
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 14
Bit 14
Bit 14
Bit 6
Bit 6
Bit 6
6
6
6
6
6
6
M68HC11E Family Data Sheet, Rev. 5.1
Bit 13
Bit 13
Bit 13
Bit 5
Bit 5
Bit 5
5
5
5
5
5
5
Indeterminate after reset
Indeterminate after reset
Indeterminate after reset
Indeterminate after reset
Indeterminate after reset
Indeterminate after reset
Bit 12
Bit 12
Bit 12
Bit 4
Bit 4
Bit 4
Address: $1011
Address: $1013
Address: $1015
Address: $1010
Address: $1012
Address: $1014
4
4
4
4
4
4
Bit 11
Bit 11
Bit 11
Bit 3
Bit 3
Bit 3
3
3
3
3
3
3
Bit 10
Bit 10
Bit 10
Bit 2
Bit 2
Bit 2
2
2
2
2
2
2
Bit 9
Bit 1
Bit 9
Bit 1
Bit 9
Bit 1
1
1
1
1
1
1
Freescale Semiconductor
Bit 0
Bit 8
Bit 0
Bit 0
Bit 0
Bit 8
Bit 0
Bit 0
Bit 0
Bit 8
Bit 0
Bit 0

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