MC68HC11E0CFNE2R Freescale Semiconductor, MC68HC11E0CFNE2R Datasheet - Page 136

• Manufacturer Part Number: MC68HC11E0CFNE2R
• Description: IC MCU 8BIT 2MHZ 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC11E0CFNE2R

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Type: ROMless
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Processor Series: HC11E
• Core: HC11
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 2 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

Timing Systems
FOC[1:5] — Force Output Comparison Bit
Bits [2:0] — Unimplemented
9.4.3 Output Compare Mask Register
Use OC1M with OC1 to specify the bits of port A that are affected by a successful OC1 compare. The bits
of the OC1M register correspond to PA[7:3].
OC1M[7:3] — Output Compare Masks
Bits [2:0] — Unimplemented
9.4.4 Output Compare Data Register
Use this register with OC1 to specify the data that is to be stored on the affected pin of port A after a
successful OC1 compare. When a successful OC1 compare occurs, a data bit in OC1D is stored in the
corresponding bit of port A for each bit that is set in OC1M.
If OC1Mx is set, data in OC1Dx is output to port A bit x on successful OC1 compares.
Bits [2:0] — Unimplemented
136
When the FOC bit associated with an output compare circuit is set, the output compare circuit
immediately performs the action it is programmed to do when an output match occurs.
Always read 0
Always read 0
Always read 0
0 = Not affected
1 = Output x action occurs
0 = OC1 disabled
1 = OC1 enabled to control the corresponding pin of port A
Address:
Address:
Reset:
Reset:
Read:
Read:
Write:
Write:
OC1M7
OC1D7
$100C
Figure 9-13. Output Compare 1 Mask Register (OC1M)
$100D
Figure 9-14. Output Compare 1 Data Register (OC1D)
Bit 7
Bit 7
0
0
= Unimplemented
= Unimplemented
OC1M6
OC1D6
6
0
6
0
M68HC11E Family Data Sheet, Rev. 5.1
OC1M5
OC1D5
5
0
5
0
OC1M4
OC1D4
4
0
4
0
OC1M3
OC1D3
3
0
3
0
2
0
2
0
1
0
1
0
Freescale Semiconductor
Bit 0
Bit 0
0
0