MCF52274CLU120 Freescale Semiconductor, MCF52274CLU120 Datasheet

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... Real-time clock (RTC) • Two programmable interrupt controllers (PIT) Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. © Freescale Semiconductor, Inc., 2009. All rights reserved. ® Document Number: MCF52277 Rev. 8, 09/2009 MCF52277 LQFP– ...

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... C Timing Specifications . . . . . . . . . . . . . . . . . . . . . . 36 5.14 DMA Timer Timing Specifications . . . . . . . . . . . . . . . . 38 5.15 DSPI Timing Specifications . . . . . . . . . . . . . . . . . . . . . 38 5.16 SBF Timing Specifications 5.17 JTAG and Boundary Scan Timing Specifications . . . . 40 5.18 Debug AC Timing Specifications . . . . . . . . . . . . . . . . . 42 6 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7 Product Documentation Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 ® Microprocessor Data Sheet, Rev. 8 Freescale Semiconductor ...

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... EPORT – Edge port module GPIO – General purpose input/output module – Inter-intergrated circuit INTC – Interrupt controller JTAG – Joint Test Action Group interface MCF5227x ColdFire Freescale Semiconductor MCF52277 BDM EMAC Divide Crossbar Switch (XBS) DSPI RTC FlexCAN GPIO INTC ...

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... LQFP ® Microprocessor Data Sheet, Rev. 8 MCF52277 • 166.67 MHz up to 83.33 MHz up to 159 128 Kbytes 8 Kbytes • 18-bit color • • • • • • • 1 • • • • • • • 196 MAPBGA Freescale Semiconductor ...

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... Ordering Information Freescale Part Number MCF52274CLU120 MCF52274 RISC Microprocessor MCF52277CVM160 MCF52277 RISC Microprocessor 3 Hardware Design Considerations 3.1 PLL Power Filtering To further enhance noise isolation, an external filter is strongly recommended for PLL analog V Figure 2 should be connected between the board V close to the dedicated PLLV pin as possible ...

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... PLLV going low by more than 0.4 V during power down or there will ® Microprocessor Data Sheet, Rev. 8 Figure 4 should be connected ADC V Pin DD 0.1 µF /SDV more than 0.4 V during power ramp-up SDV must power DD DD Freescale Semiconductor DD (2.5V DD powers up ...

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... These current measurements are taken after executing a STOP instruction. Table 4. Current Consumption in Low-Power Modes Mode Voltage Supply IV DD RUN Power (mW WAIT Power (mW) MCF5227x ColdFire Freescale Semiconductor Idle (audio Button Slideshow image) Demo 59.2 84.7 25.73 35.3 18.57 21.8 207.135 282 ...

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... V). Tests DD RUN WAIT DOZE STOP 0 STOP 1 STOP 2 STOP 3 4 (LIMP) Freescale Semiconductor ...

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... Table 5. Special-Case Default Signal Functionality Table 6. MCF5227x Signal Information and Muxing Signal Name GPIO RESET — RSTOUT — EXTAL — XTAL — BOOTMOD[1:0] — MCF5227x ColdFire Freescale Semiconductor States,” NOTE NOTE Pin Default Signal FB_BE/BWE[3:0] FB_BE/BWE[3:0] FB_CS[3:0] FB_CS[3:0] FB_OE FB_OE FB_TA FB_TA FB_R/W ...

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... U I SDVDD 115 — O SDVDD 68 — O SDVDD 15 — O SDVDD 46 — O SDVDD 47 — O SDVDD 17 — O SDVDD 40 — O SDVDD 41 — O SDVDD 18 — I/O SDVDD 28, 58 — O SDVDD 48 Freescale Semiconductor C11, D11 B14, C13 D14 E11–E14, G12, H11 P1 B11, A11 D10 C10 N8 H12 J2 ...

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... PLCDCTL3 LCD_OE LCD_FLM/ PLCDCTL2 LCD_VSYNC LCD_LP/ PLCDCTL1 LCD_HSYNC LCD_LSCLK PLCDCTL0 USB_DM — USB_DP — RTC_EXTAL — RTC_XTAL — MCF5227x ColdFire Freescale Semiconductor Alternate 1 Alternate 2 — — — — 4 External Interrupts Port — — DREQ0 DSPI_PCS4 USB_CLKIN SSI_CLKIN 6 LCD Controller LCD_D[11:10] — ...

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... I EVDD 97 — O EVDD 98 — O EVDD 95 — I EVDD 96 — I EVDD 163 — I EVDD 164 — I EVDD 165 — I EVDD 166 — O EVDD — L9, M9, N9, P9 — O EVDD — L10, M10, N10, Freescale Semiconductor M13, M14 M12 K12 J12 L12 K13 P10 ...

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... DSPI or SBF signal functionality is controlled by RESET. When asserted, these pins are configured for serial boot; when negated, the pins are configured for DSPI. 8 Pull-up when the serial boot facility (SBF) controls the pin. MCF5227x ColdFire Freescale Semiconductor Alternate 1 Alternate 2 — — ...

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... SD_VDD 113 VSS 112 111 EVDD 110 BOOTMOD1 109 BOOTMOD0 108 VDD_OSC 107 VSS_OSC 106 EXTAL 105 XTAL 104 VDD_PLL 103 RESET 102 RSTOUT 101 VDD_RTC 100 RTC_EXTAL 99 RTC_XTAL 98 U0RTS 97 U0CTS 96 U0RXD 95 U0TXD 94 EVDD 93 VSS 92 VSS_ADC 91 VDD_ADC 90 ADC_IN0 89 ADC_IN1 Freescale Semiconductor ...

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... The electrical specifications are preliminary and are from previous designs or design simulations. These specifications may not be fully tested or guaranteed at this early stage of the product life cycle, however for production silicon these specifications will be met. Finalized specifications will be published after complete characterization and device qualifications have been completed. MCF5227x ColdFire Freescale Semiconductor ...

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... Microprocessor Data Sheet, Rev Value Unit –0.5 to +2.0 V –0.3 to +4.0 V –0 –0 –0 –0 –0 °C – °C –55 to +150 Specifications.” Absolute maximum ratings , the injection current may flow out of DD load will shunt current DD Freescale Semiconductor ...

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... constant pertaining to the particular part. K can be determined from for a known T . Using this value of K, the values for any value MCF5227x ColdFire Freescale Semiconductor Table 8. Thermal Characteristics Symbol Four layer board (2s2p) θ Four layer board (2s2p) and power dissipation specifications in the system design to prevent device JmA ) in ° ...

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... DD EV 3.0 3.6 DD SDV DD 1.7 1.95 2.25 2.75 3.0 3.6 3.0 3.6 DD 3 – 0.3 0 – 0.4 — — 0.4 OL SDV IH 1.35 SDV + 0.3 DD 1.7 SDV + 0 SDV + 0.3 DD SDV IL V – 0.3 0. – 0.3 0 – 0.3 0.8 SS Freescale Semiconductor Unit ...

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... All other modes (External, Limp) 3,6 7 PLL Lock Time 3 8 Duty cycle of reference 9 XTAL Current 10 Total on-chip stray capacitance on XTAL 11 Total on-chip stray capacitance on EXTAL 12 Crystal capacitive load MCF5227x ColdFire Freescale Semiconductor Symbol SDV SDV 1 Max. IL Table 11. PLL Electrical Characteristics Symbol f ref_crystal f ref_ext f sys f ...

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... Typical Max 3.0 — 3.6 0 — V DDA — 700 — — 1 — — — 12 — — 125 ±8 ±24 — ±2 ±24 — 2 — — V DDA Freescale Semiconductor Unit sys % f sys % f sys sys/2 MHz . sys Unit bits kS/s 1 lsb 1 lsb MHz V ...

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... Clock Period (FB_CLK) FB2 Address, Data, and Control Output Valid (FB_A[23:0], FB_D[31:0], FB_CS[5:0], FB_R/W, FB_TS, FB_BE/BWE[3:0] and FB_OE) FB3 Address, Data, and Control Output Hold (FB_A[23:0], FB_D[31:0], FB_CS[5:0], FB_R/W, FB_TS, FB_BE/BWE[3:0], and FB_OE) MCF5227x ColdFire Freescale Semiconductor Symbol t ADC t ADS t AMS ...

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... FB_TS FB6 FB_TA Figure 9. FlexBus Read Timing ® Microprocessor Data Sheet, Rev. 8 Symbol Min Max Unit t 3.5 — ns DVFBCH t 0 — ns DIFBCH t 4 — ns CVFBCH t 0 — ns CIFBCH Section 5.7.2.2, “DDR SDRAM AC Timing S2 S3 FB3 FB5 FB4 FB7 Freescale Semiconductor Notes ...

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... SD3 Pulse Width Low SD4 Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_BA, SD_CS[1:0] - Output Valid SD5 Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_BA, SD_CS[1:0] - Output Hold SD6 SD_SDR_DQS Output Valid SD7 SD_DQS[3:2] input setup relative to SD_CLK MCF5227x ColdFire Freescale Semiconductor S0 S1 FB_CLK FB1 ADDR[23:0] FB2 ADDR[31:X] ...

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... SD12 WD1 WD2 Figure 11. SDR Write Timing ® Microprocessor Data Sheet, Rev. 8 Min Max Unit Does not apply. 0.5×SD_CLK fixed width. 0.25 × — ns SD_CLK 1.0 — ns 0.5 × SD_CLK — 1.5 — ns SD2 SD3 WD3 WD4 Freescale Semiconductor Notes 6 7 ...

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... Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_CS[1:0] - Output Hold DD6 Write Command to first DQS Latching Transition DD7 Data and Data Mask Output Setup (DQ→DQS) Relative to DQS (DDR Write Mode) MCF5227x ColdFire Freescale Semiconductor SD1 SD5 3/4 MCLK Reference COL Board Delay Board Delay SD10 Figure 12 ...

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... Data input hold is derived from each DQS clock edge. It begins with a DQS transition and ends when the first data line becomes invalid. MCF5227x ColdFire 26 Symbol Min t 1.0 DQDMI t — DVDQ 0.25 × SD_CLK t DIDQ + 0.5ns 0.5 DQLSDCH ® Microprocessor Data Sheet, Rev. 8 Max Unit Notes 7 — — ns — ns Freescale Semiconductor ...

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... SD_CLK SD_CLK SD_CSn, SD_WE, SD_RAS, SD_CAS A[13:0] SD_DQS[3:2] SD_DM[3:2] D[31:16] MCF5227x ColdFire Freescale Semiconductor DD1 DD2 DD5 CMD DD4 ROW COL DD6 WD1 WD2 WD3 WD4 Figure 13. DDR Write Timing ® Microprocessor Data Sheet, Rev. 8 Electrical Characteristics DD3 DD11 DD7 DD8 ...

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... Microprocessor Data Sheet, Rev. 8 DD2 DD3 CL=2 CL=2.5 DD9 DQS Read DQS Read Postamble Preamble DD10 WD1 WD2 WD3 WD4 DQS Read DQS Read Preamble Postamble WD1 WD2 WD3 WD4 Min Max 1.05 1.45 –0.3 SD_VDD + 0.3 0.7 SD_VDD + 0.6 1.05 1. Freescale Semiconductor Unit ...

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... R8 RSTOUT invalid to Configuration Override High Impedance 1 During low power STOP, the synchronizers for the RESET input are bypassed and RESET is asserted asynchronously to the system. Thus, RESET must be held a minimum of 100 ns. MCF5227x ColdFire Freescale Semiconductor Table 17. GPIO Timing Characteristic Figure 16. GPIO Timing Characteristic ® ...

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... LCD_LSCLK is equal to the pixel clock divided by bus width. The polarity of LCD_LSCLK and LCD_D signals can also be programmed. LCD_LSCLK LCD_D[17:0] Figure 18. LCD_LSCLK to LCD_D[17:0] timing diagram MCF5227x ColdFire NOTE Table 19. LCD_LSCLK Timing Characteristic ® Microprocessor Data Sheet, Rev Min Max Unit 25 2000 ns 11 — — ns Freescale Semiconductor R8 ...

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... Note the LCD_LSCLK period. LCD_VSYNC, LCD_HSYNC, and LCD_OE can be programmed as active high or active low. In Figure 19, all 3 signals are active low. LCD_LSCLK can be programmed to be deactivated during the LCD_VSYNC pulse or the LCD_OE deasserted period. In Note: XMAX is defined in number of pixels in one line. MCF5227x ColdFire Freescale Semiconductor Non-display Region XMAX ...

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... Note: Falling of LCD_PS aligns with rising edge of LCD_CLS. Note: LCD_REV toggles in every LCD_HSYN period. MCF5227x ColdFire Figure 20. Sharp TFT Panel Timing Table 21. Sharp TFT Panel Timing Min — ® Microprocessor Data Sheet, Rev. 8 XMAX D320 Value 1 HWAIT1+1 HWAIT2 + 4 CLS_RISE_DELAY+1 CLS_HI_WIDTH+1 PS_RISE_DELAY REV_TOGGLE_DELAY+1 Freescale Semiconductor Unit ...

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... Input Low Input Differential Differential Common Mode Range Single Ended Receive Threshold Single Ended Receive Hysteresis Output High Output Low Differential Output Crossover MCF5227x ColdFire Freescale Semiconductor T1 T3 XMAX Figure 21. Non-TFT Mode Panel Timing Table 22. Non-TFT Mode Panel Timing Characteristic Condition Symbol ...

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... Typ Max Unit 330 360 640 ps 100 140 210 ps Min Typ Max Unit 75 — 300 ns 75 — 300 ns 80 — 125 % 1 Min Max Unit Notes 4 × 1/f — ns SYS 45% 55% t MCLK 4 × 1/f — ns SYS 45% 55% t BCLK Freescale Semiconductor 2 3 ...

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... SSI_BCLK to SSI_TXD / SSI_FS output invalid / high impedence S17 SSI_RXD setup before SSI_BCLK S18 SSI_RXD hold after SSI_BCLK 1 All timings specified with a capactive load of 25 pF. MCF5227x ColdFire Freescale Semiconductor 1 Symbol Table 27. SSI Timing—Slave Modes Symbol t BCLK ® Microprocessor Data Sheet, Rev. 8 ...

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... S18 Figure 23. SSI Timing—Slave Modes C input timing parameters shown in Figure 2 C Input Timing Specifications between SCL and SDA Characteristic = 0 2 ® Microprocessor Data Sheet, Rev S10 S8 S16 S14 S16 24. Min Max Unit 2 — t cyc 8 — t cyc — — ns Freescale Semiconductor ...

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... I2C_SCL or I2C_SDA take to reach a high level depends on external signal capacitance and pull-up resistor values. 3 Specified at a nominal 50-pF load. Figure 24 shows timing for the values in I2C_SCL I1 I2C_SDA MCF5227x ColdFire Freescale Semiconductor Characteristic = 2 0 output timing parameters shown in C Output Timing Specifications between SCL and SDA Characteristic = 0 ...

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... Microprocessor Data Sheet, Rev. 8 Min Max Unit 3 — t CYC 1 — t CYC 1 Max Unit — ns SYS (tsck ÷ 2 – 2.0 — – 3.0 — — ns — — — — — Freescale Semiconductor Notes ...

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... Figure 26. DSPI Classic SPI Timing—Slave Mode 5.16 SBF Timing Specifications The Serial Boot Facility (SBF) provides a means to read configuration information and system boot code from a broad array of SPI-compatible EEPROMs, flashes, FRAMs, nVSRAMs, etc. MCF5227x ColdFire Freescale Semiconductor DS3 DS2 DS2 DS7 DS8 ...

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... SBFCK – 2.0 — ns SBFCK — — — — ns SB4 Last Data SB5 Last Data Symbol Min Max f DC 1/4 JCYC t 4 — JCYC t 26 — JCW JCRF t 4 — BSDST t 26 — BSDHT BSDV BSDZ Freescale Semiconductor 1 Unit f sys/2 t CYC ...

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... JTAG_EN is expected static signal. Hence, specific timing is not associated with it TCLK (input) J4 TCLK V IL Data Inputs Data Outputs Data Outputs Data Outputs MCF5227x ColdFire Freescale Semiconductor Figure 28. Test Clock Input Timing J5 Input Data Valid Figure 29. Boundary Scan (JTAG) Timing ® Microprocessor Data Sheet, Rev. 8 ...

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... Figure 31. TRST Timing Figure Table 34. Debug AC Timing Specification Characteristic ® Microprocessor Data Sheet, Rev J10 Output Data Valid Output Data Valid 32. Min Max Units 1 1 1/f SYS — 3.0 ns 1.5 — — PSTCLK 4 — PSTCLK 5 — PSTCLK 1 — PSTCLK Freescale Semiconductor ...

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... LQFP MCF52277 196 MAPBGA 7 Product Documentation Documentation is available from a local Freescale distributor, a Freescale sales office, the Freescale Literature Distribution Center, or through the Freescale world-wide web address at http://www.freescale.com/coldfire. MCF5227x ColdFire Freescale Semiconductor D0 D1 Figure 32. Real-Time Trace AC Timing D5 Current D4 Past Figure 33. BDM Serial Port AC Timing Table 35 ...

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... MCF5227x ColdFire 44 Summary of Changes Initial public revision. Corrected MCF52274 order number from MCF52274CAB120 to MCF52274CLU120 in Table 2 Corrected MCF52277CVM166 part number to MCF52277CVM160 in Although, this device has a maximum rated frequency of 166.67 MHz. Added data to Section 3.5, “Power Consumption Changed document type from Data Sheet: Advance Information to Data Sheet: ...

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... MCF5227x ColdFire Freescale Semiconductor ® Microprocessor Data Sheet, Rev. 8 Revision History 45 ...

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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...