MC908LJ24CFUE Freescale Semiconductor, MC908LJ24CFUE Datasheet - Page 113

IC MCU 24K FLASH 8MHZ SPI 64-QFP

MC908LJ24CFUE

Manufacturer Part Number
MC908LJ24CFUE
Description
IC MCU 24K FLASH 8MHZ SPI 64-QFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC908LJ24CFUE

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, IRSCI, SPI
Peripherals
LCD, LVD, POR, PWM
Number Of I /o
40
Program Memory Size
24KB (24K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-QFP
Processor Series
HC08LJ
Core
HC08
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
SCI/SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
48
Number Of Timers
4
Operating Supply Voltage
3.3 V, 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68EML08LJLKE, ZK-HC08LX-A, M68CBL05CE
Minimum Operating Temperature
- 40 C
On-chip Adc
6-ch x 10-bit
Controller Family/series
HC08
No. Of I/o's
40
Ram Memory Size
768Byte
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
I2C, SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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MC68HC908LJ24/LK24 — Rev. 2.1
Freescale Semiconductor
Addr.
$003A
$003B
$0036
$0037
$0038
$0039
NOTES:
1. When AUTO = 0, PLLIE is forced clear and is read-only.
2. When AUTO = 0, PLLF and LOCK read as clear.
3. When AUTO = 1, ACQ is read-only.
4. When PLLON = 0 or VRS7:VRS0 = $0, BCS is forced clear and is read-only.
5. When PLLON = 1, the PLL programming register is read-only.
6. When BCS = 1, PLLON is forced set and is read-only.
PLL VCO Range Select
PLL Bandwidth Control
PLL Reference Divider
Register Name
PLL Control Register
PLL Multiplier Select
PLL Multiplier Select
Select Register
Register High
Register Low
Register
Register
(PBWC)
(PMSH)
(PMRS)
(PMDS)
(PMSL)
(PTCL)
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
Write:
Figure 8-2. CGM I/O Register Summary
AUTO
PLLIE
MUL7
VRS7
Bit 7
0
0
0
0
0
0
0
0
Clock Generator Module (CGM)
= Unimplemented
LOCK
MUL6
VRS6
PLLF
6
0
0
0
0
1
1
0
0
PLLON
MUL5
VRS5
ACQ
5
1
0
0
0
0
0
0
0
MUL4
VRS4
BCS
4
0
0
0
0
0
0
0
0
0
MUL11
PRE1
MUL3
VRS3
RDS3
R
3
0
0
0
0
0
0
0
Clock Generator Module (CGM)
= Reserved
MUL10
MUL2
VRS2
RDS2
PRE0
2
0
0
0
0
0
0
0
Functional Description
MUL9
MUL1
RDS1
VPR1
VRS1
1
0
0
0
0
0
0
0
Data Sheet
MUL8
MUL0
RDS0
VPR0
VRS0
Bit 0
R
0
0
0
0
0
1
113

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