MC908LJ24CFUE Freescale Semiconductor, MC908LJ24CFUE Datasheet - Page 235

• Manufacturer Part Number: MC908LJ24CFUE
• Description: IC MCU 24K FLASH 8MHZ SPI 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908LJ24CFUE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, IRSCI, SPI
• Peripherals: LCD, LVD, POR, PWM
• Number Of I /o: 40
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Processor Series: HC08LJ
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V, 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68EML08LJLKE, ZK-HC08LX-A, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 6-ch x 10-bit
• Controller Family/series: HC08
• No. Of I/o's: 40
• Ram Memory Size: 768Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

12.10.4 RTC Control Register 2 (RTCCR2)
MC68HC908LJ24/LK24 — Rev. 2.1
Freescale Semiconductor
†† Reset by POR only.
* COMEN and RTCE bits are write-protected; unprotect by a write sequence to RTCWE[1:0] in RTCCOMR.
Address:
SECIE — Second Interrupt Enable
TB1IE — Timebase 1 Interrupt Enable
TB2IE — Timebase 2 Interrupt Enable
The RTC control register 2 (RTCCR2) contains control and clock
selection bits for RTC operation.
COMEN — RTC Compensation Enable
Reset:
Read:
Write:
This read/write bit enables the second flag, SECF, to generate CPU
interrupt requests. Reset clears the SECIE bit.
This read/write bit enables the timebase1 flag, TB1F, to generate
CPU interrupt requests. Reset clears the TB1IE bit.
This read/write bit enables the timebase2 flag, TB2F, to generate
CPU interrupt requests. Reset clears the TB2IE bit.
This read/write bit enables the clock compensation mechanism for
CGMXCLK frequency errors. Reset has no effect on COMEN bit.
1 = SECF enabled to generate CPU interrupt
0 = SECF not enabled to generate CPU interrupt
1 = TB1F enabled to generate CPU interrupt
0 = TB1F not enabled to generate CPU interrupt
1 = TB2F enabled to generate CPU interrupt
0 = TB2F not enabled to generate CPU interrupt
1 = Compensation mechanism enabled
0 = Compensation mechanism not enabled
COMEN*
$0043
U
Figure 12-9. RTC Control Register 2 (RTCCR2)
Real Time Clock (RTC)
CHRCLR
= Unimplemented
0
0
CHRE
0
RTCE*
0
††
TBH
0
0
0
Real Time Clock (RTC)
0
0
RTC Registers
Data Sheet
0
0
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