MC908LJ24CFUE Freescale Semiconductor, MC908LJ24CFUE Datasheet - Page 345

IC MCU 24K FLASH 8MHZ SPI 64-QFP

MC908LJ24CFUE

Manufacturer Part Number
MC908LJ24CFUE
Description
IC MCU 24K FLASH 8MHZ SPI 64-QFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC908LJ24CFUE

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, IRSCI, SPI
Peripherals
LCD, LVD, POR, PWM
Number Of I /o
40
Program Memory Size
24KB (24K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-QFP
Processor Series
HC08LJ
Core
HC08
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
SCI/SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
48
Number Of Timers
4
Operating Supply Voltage
3.3 V, 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68EML08LJLKE, ZK-HC08LX-A, M68CBL05CE
Minimum Operating Temperature
- 40 C
On-chip Adc
6-ch x 10-bit
Controller Family/series
HC08
No. Of I/o's
40
Ram Memory Size
768Byte
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
I2C, SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Manufacturer
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MC68HC908LJ24/LK24 — Rev. 2.1
Freescale Semiconductor
Addr.
$003D
Addr.
$003D
$003E
$003E
ADC Data Register High
ADC Data Register High
ADC Data Register Low
ADC Data Register Low
Register Name
Register Name
Figure 16-8. ADRH and ADRL in Left Justified Sign Data Mode
(ADRH)
(ADRH)
(ADRL)
(ADRL)
Figure 16-7. ADRH and ADRL in Left Justified Mode
In left justified mode the ADRH holds the eight most significant bits
(MSBs), and the ADRL holds the two least significant bits (LSBs), of the
10-bit result. The ADRH and ADRL are updated each time a single
channel ADC conversion completes. Reading ADRH latches the
contents of ADRL. Until ADRL is read all subsequent ADC results will be
lost. (See
In left justified sign mode the ADRH holds the eight MSBs with the MSB
complemented, and the ADRL holds the two least significant bits (LSBs),
of the 10-bit result. The ADRH and ADRL are updated each time a single
channel ADC conversion completes. Reading ADRH latches the
contents of ADRL. Until ADRL is read all subsequent ADC results will be
lost. (See
Mode.)
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Bit 7
Bit 7
AD9
AD1
AD9
AD1
Analog-to-Digital Converter (ADC)
R
R
R
R
0
0
0
0
Figure 16-7 . ADRH and ADRL in Left Justified
Figure 16-8 . ADRH and ADRL in Left Justified Sign Data
AD8
AD0
AD8
AD0
R
R
R
R
6
0
0
6
0
0
AD7
AD7
R
R
R
R
5
0
0
0
5
0
0
0
AD6
AD6
R
R
R
R
4
0
0
0
4
0
0
0
AD5
AD5
R
R
R
R
3
0
0
0
3
0
0
0
Analog-to-Digital Converter (ADC)
AD4
AD4
R
R
R
R
2
0
0
0
2
0
0
0
AD3
AD3
R
R
R
R
1
0
0
0
1
0
0
0
Mode.)
I/O Registers
Data Sheet
Bit 0
Bit 0
AD2
AD2
R
R
R
R
0
0
0
0
0
0
345

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