MC68HC11E1CFNE2R Freescale Semiconductor, MC68HC11E1CFNE2R Datasheet - Page 143

IC MCU 8BIT 2MHZ 52-PLCC

MC68HC11E1CFNE2R

Manufacturer Part Number
MC68HC11E1CFNE2R
Description
IC MCU 8BIT 2MHZ 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheets

Specifications of MC68HC11E1CFNE2R

Core Processor
HC11
Core Size
8-Bit
Speed
3MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Type
ROMless
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Controller Family/series
68HC11
No. Of I/o's
38
Eeprom Memory Size
512Byte
Ram Memory Size
512Byte
Cpu Speed
2MHz
No. Of Timers
1
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Processor Series
HC11E
Core
HC11
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI, SPI
Maximum Clock Frequency
2 MHz
Number Of Programmable I/os
38
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Program Memory Size
-
Lead Free Status / Rohs Status
 Details

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PEDGE — Pulse Accumulator Edge Control Bit
DDRA3 — Data Direction for Port A Bit 3
I4/O5 — Input Capture 4/Output Compare Bit
RTR[1:0] — RTI Interrupt Rate Select Bits
9.6 Computer Operating Properly (COP) Watchdog Function
The clocking chain for the COP function, tapped off of the main timer divider chain, is only superficially
related to the main timer system. The CR[1:0] bits in the OPTION register and the NOCOP bit in the
CONFIG register determine the status of the COP function. One additional register, COPRST, is used to
arm and clear the COP watchdog reset system. Refer to
detailed discussion of the COP function.
9.7 Pulse Accumulator
The M68HC11 Family of MCUs has an 8-bit counter that can be configured to operate either as a simple
event counter or for gated time accumulation, depending on the state of the PAMOD bit in the PACTL
register. Refer to the pulse accumulator block diagram,
counter is clocked to increasing values by an external pin. The maximum clocking rate for the external
event counting mode is the E clock divided by two. In gated time accumulation mode, a free-running
E-clock divide-by-64 signal drives the 8-bit counter, but only while the external PAI pin is activated. Refer
to
Pulse accumulator control bits are also located within two timer registers, TMSK2 and TFLG2, as
described in the following paragraphs.
Freescale Semiconductor
Table
Refer to
Refer to
Refer to
These two bits determine the rate at which the RTI system requests interrupts. The RTI system is
driven by an E divided by 2
These two control bits select an additional division factor. Refer to
9-6. The pulse accumulator counter can be read or written at any time.
9.7 Pulse
Chapter 6 Parallel Input/Output (I/O)
9.7 Pulse
Frequency
12.0 MHz
4.0 MHz
8.0 MHz
Crystal
Accumulator.
Accumulator.
13
rate clock that is compensated so it is independent of the timer prescaler.
Table 9-6. Pulse Accumulator Timing
E Clock
1 MHz
2 MHz
3 MHz
M68HC11E Family Data Sheet, Rev. 5.1
Cycle Time
1000 ns
Ports.
500 ns
333 ns
Computer Operating Properly (COP) Watchdog Function
Figure
Chapter 5 Resets and Interrupts
9-24. In the event counting mode, the 8-bit
21.33 µs
E ÷ 64
64 µs
32 µs
Table
9-5.
16.384 ms
Overflow
8.192 ms
5.461 ms
PACNT
for a more
143

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