MC68HC11E1CFNE2R Freescale Semiconductor, MC68HC11E1CFNE2R Datasheet - Page 157

IC MCU 8BIT 2MHZ 52-PLCC

MC68HC11E1CFNE2R

Manufacturer Part Number
MC68HC11E1CFNE2R
Description
IC MCU 8BIT 2MHZ 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheets

Specifications of MC68HC11E1CFNE2R

Core Processor
HC11
Core Size
8-Bit
Speed
3MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Type
ROMless
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Controller Family/series
68HC11
No. Of I/o's
38
Eeprom Memory Size
512Byte
Ram Memory Size
512Byte
Cpu Speed
2MHz
No. Of Timers
1
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Processor Series
HC11E
Core
HC11
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI, SPI
Maximum Clock Frequency
2 MHz
Number Of Programmable I/os
38
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Program Memory Size
-
Lead Free Status / Rohs Status
 Details

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68HC11E1CFNE2R
Manufacturer:
Freescale Semiconductor
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10.10 MC68L11E9/E20 Control Timing
Freescale Semiconductor
Frequency of operation
E-clock period
Crystal frequency
External oscillator frequency
Processor control setup time
Reset input pulse width
Mode programming setup time
Mode programming hold time
Interrupt pulse width, IRQ edge-sensitive mode
Wait recovery startup time
Timer pulse width input capture pulse accumulator input
1. V
2. RESET is recognized during the first clock cycle it is held low. Internal circuitry then drives the pin low for four clock cycles,
t
To guarantee external reset vector
Minimum input time (can be pre-empted by internal reset)
PW
PW
PCSU
otherwise noted
releases the pin, and samples the pin level two cycles later to determine the source of the interrupt. Refer to
Resets and Interrupts
DD
IRQ
TIM
= 3.0 Vdc to 5.5 Vdc, V
Notes
= 1/4 t
= t
= t
1. Rising edge sensitive input
2. Falling edge sensitive input
3. Maximum pulse accumulator clocking rate is E-clock frequency divided by 2.
PA[2:0]
PA[2:0]
CYC
CYC
PA7
PA7
:
CYC
(1) (3)
(2) (3)
+ 20 ns
+ 20 ns
(1)
(2)
+ 75 ns
Characteristic
for further detail.
SS
= 0 Vdc, T
PW
TIM
(1) (2)
M68HC11E Family Data Sheet, Rev. 5.1
A
Figure 10-2. Timer Inputs
= T
L
to T
H
, all timing is shown with respect to 20% V
Symbol
PW
PW
PW
t
f
t
t
PCSU
t
t
XTAL
WRS
4 f
MPS
MPH
CYC
f
RSTL
o
IRQ
TIM
o
1000
1020
1020
Min
325
dc
dc
10
8
1
2
1.0 MHz
MC68L11E9/E20 Control Timing
Max
1.0
4.0
4.0
4
DD
Min
500
200
520
520
dc
dc
10
and 70% V
8
1
2
2.0 MHz
Max
2.0
8.0
8.0
4
DD
Chapter 5
, unless
MHz
MHz
MHz
Unit
t
t
t
CYC
CYC
CYC
ns
ns
ns
ns
ns
157

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