MC68HC11E1CFNE2R Freescale Semiconductor, MC68HC11E1CFNE2R Datasheet - Page 172

• Manufacturer Part Number: MC68HC11E1CFNE2R
• Description: IC MCU 8BIT 2MHZ 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC11E1CFNE2R

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Type: ROMless
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Controller Family/series: 68HC11
• No. Of I/o's: 38
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 512Byte
• Cpu Speed: 2MHz
• No. Of Timers: 1
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC11E
• Core: HC11
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 2 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

10.18 MC68L11E9/E20 Serial Peirpheral Interface Characteristics
172
Electrical Characteristics
1. V
2. Time to data active from high-impedance state
3. Assumes 100 pF load on SCK, MOSI, and MISO pins
Num
10
11
otherwise noted
1
2
3
4
5
6
7
8
9
DD
= 3.0 Vdc to 5.5 Vdc, V
Frequency of operation
E-clock period
Operating frequency
Cycle time
Enable lead time
Enable lag time
Clock (SCK) high time
Clock (SCK) low time
Data setup time (inputs)
Data hold time (inputs)
Slave access time
Disable time (hold time
Data valid
Data hold time (outputs)
E clock
Master
Slave
Master
Slave
Slave
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
CPHA = 0
CPHA = 1
to high-impedance state)
Slave
(after enable edge)
Characteristic
(3)
(after enable edge)
(2)
(2)
SS
(1)
= 0 Vdc, T
M68HC11E Family Data Sheet, Rev. 5.1
A
= T
t
t
t
t
w(SCKH)m
Symbol
w(SCKL)m
w(SCKH)s
w(SCKL)s
t
L
t
t
CYC(m)
f
CYC(s)
t
t
lead(s)
f
t
t
t
op(m)
su(m)
lag(s)
t
to T
op(s)
su(s)
CYC
h(m)
t
h(s)
t
f
t
dis
t
ho
o
a
v
H
, all timing is shown with respect to 20% V
t
t
t
t
CYC
CYC
CYC
CYC
f
Min
500
o
1/2
1/2
40
40
40
40
dc
dc
—
—
/32
2
1
1
1
0
0
0
–30
–30
–30
–30
E9
16 t
16 t
Max
f
2.0
32
50
50
60
60
—
o
—
—
—
—
—
—
—
—
—
—
f
o
/2
CYC
CYC
t
t
t
t
CYC
CYC
CYC
CYC
f
o
Min
500
1/2
1/2
/128
dc
dc
40
40
40
40
—
—
2
1
1
1
0
0
0
–30
–30
–30
–30
DD
Freescale Semiconductor
E20
and 70% V
64 t
64 t
Max
128
f
2.0
o
50
50
60
60
—
—
—
—
—
—
—
—
—
—
—
f
/2
o
CYC
CYC
DD
, unless
MHz
Unit
MHz
t
t
t
CYC
CYC
CYC
ns
ns
ns
ns
ns
ns
ns
ns
ns