MC68HC11E1CFNE2R Freescale Semiconductor, MC68HC11E1CFNE2R Datasheet - Page 37

IC MCU 8BIT 2MHZ 52-PLCC

MC68HC11E1CFNE2R

Manufacturer Part Number
MC68HC11E1CFNE2R
Description
IC MCU 8BIT 2MHZ 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheets

Specifications of MC68HC11E1CFNE2R

Core Processor
HC11
Core Size
8-Bit
Speed
3MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Type
ROMless
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Controller Family/series
68HC11
No. Of I/o's
38
Eeprom Memory Size
512Byte
Ram Memory Size
512Byte
Cpu Speed
2MHz
No. Of Timers
1
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Processor Series
HC11E
Core
HC11
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI, SPI
Maximum Clock Frequency
2 MHz
Number Of Programmable I/os
38
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Program Memory Size
-
Lead Free Status / Rohs Status
 Details

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68HC11E1CFNE2R
Manufacturer:
Freescale Semiconductor
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Part Number:
MC68HC11E1CFNE2R2
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Freescale Semiconductor
1. SCP2 adds ÷39 to SCI prescaler and is present only in MC68HC(7)11E20.
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Addr.
Pulse Accumulator Control Regis-
Serial Communications Data Reg-
Serial Peripheral Control Register
Serial Peripheral Status Register
Serial Peripheral Data I/O Regis-
Pulse Accumulator Count Regis-
Analog-to-Digital Control Status
Serial Communications Control
Serial Communications Control
Serial Communications Status
Register Name
Timer Interrupt Flag 2
Register 1 (SCCR1)
Register 2 (SCCR2)
Baud Rate Register
Register (ADCTL)
Figure 2-7. Register and Control Bit Assignments (Sheet 4 of 6)
Register (SCSR)
See page 142.
See page 142.
See page 146.
See page 123.
See page 124.
See page 125.
See page 113.
See page 110.
See page 111.
See page 112.
See page 110.
See page 62.
ister (SCDR)
ter (PACNT)
ter (PACTL)
ter (SPDR)
(TFLG2)
(SPCR)
(BAUD)
(SPSR)
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
M68HC11E Family Data Sheet, Rev. 5.1
I = Indeterminate after reset
DDRA7
TCLR
TDRE
R7/T7
Bit 7
CCF
SPIE
Bit 7
SPIF
TOF
Bit 7
TIE
R8
0
0
0
0
0
0
1
0
I
= Unimplemented
SCP2
WCOL
PAEN
R6/T6
Bit 6
RTIF
TCIE
SPE
Bit 6
TC
T8
6
0
0
0
0
0
0
1
0
I
(1)
PAMOD
PAOVF
DWOM
RDRF
SCAN
SCP1
R5/T5
Bit 5
Bit 5
RIE
5
0
0
0
0
0
0
0
0
Indeterminate after reset
Indeterminate after reset
Indeterminate after reset
PEDGE
MODF
MSTR
R4/T4
MULT
SCP0
Bit 4
PAIF
IDLE
Bit 4
ILIE
M
R
4
0
0
0
0
0
0
0
0
Indeterminate after reset
= Reserved
DDRA3
WAKE
CPOL
RCKB
R3/T3
Bit 3
Bit 3
OR
CD
TE
3
0
0
0
0
0
0
0
0
CPHA
U = Unaffected
SCR2
R2/T2
I4/O5
Bit 2
Bit 2
RE
NF
CC
U
2
0
0
1
0
0
0
0
R1/T1
RTR1
SPR1
SCR1
Bit 1
RWU
Bit 1
FE
CB
U
U
1
0
0
0
0
0
0
Memory Map
SCR0
R0/T0
RTR0
SPR0
Bit 0
Bit 0
Bit 0
SBK
CA
U
U
0
0
0
0
0
0
37

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