MC68HC11E1CFNE3R Freescale Semiconductor, MC68HC11E1CFNE3R Datasheet - Page 112

• Manufacturer Part Number: MC68HC11E1CFNE3R
• Description: MCU 8-BIT 512 RAM 3MHZ 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC11E1CFNE3R

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Type: ROMless
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Processor Series: HC11E
• Core: HC11
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 3 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

Serial Communications Interface (SCI)
7.7.4 Serial Communication Status Register
The SCSR provides inputs to the interrupt logic circuits for generation of the SCI system interrupt.
TDRE — Transmit Data Register Empty Flag
TC — Transmit Complete Flag
RDRF — Receive Data Register Full Flag
IDLE — Idle Line Detected Flag
OR — Overrun Error Flag
NF — Noise Error Flag
112
This flag is set when SCDR is empty. Clear the TDRE flag by reading SCSR with TDRE set and then
writing to SCDR.
This flag is set when the transmitter is idle (no data, preamble, or break transmission in progress).
Clear the TC flag by reading SCSR with TC set and then writing to SCDR.
This flag is set if a received character is ready to be read from SCDR. Clear the RDRF flag by reading
SCSR with RDRF set and then reading SCDR.
This flag is set if the RxD line is idle. Once cleared, IDLE is not set again until the RxD line has been
active and becomes idle again. The IDLE flag is inhibited when RWU = 1. Clear IDLE by reading SCSR
with IDLE set and then reading SCDR.
OR is set if a new character is received before a previously received character is read from SCDR.
Clear the OR flag by reading SCSR with OR set and then reading SCDR.
NF is set if majority sample logic detects anything other than a unanimous decision. Clear NF by
reading SCSR with NF set and then reading SCDR.
0 = SCDR busy
0 = SCDR empty
0 = Transmitter busy
1 = Transmitter idle
0 = SCDR empty
1 = SCDR full
0 = RxD line active
1 = RxD line idle
0 = No overrun
1 = Overrun detected
0 = Unanimous decision
1 = Noise detected
Address:
Reset:
Read:
Write:
Figure 7-6. Serial Communications Status Register (SCSR)
$102E
TDRE
Bit 7
1
= Unimplemented
TC
6
1
M68HC11E Family Data Sheet, Rev. 5.1
RDRF
5
0
IDLE
4
0
OR
3
0
NF
2
0
FE
1
0
Freescale Semiconductor
Bit 0
0