MC68HC11E1CFNE3R Freescale Semiconductor, MC68HC11E1CFNE3R Datasheet - Page 113

MCU 8-BIT 512 RAM 3MHZ 52-PLCC

MC68HC11E1CFNE3R

Manufacturer Part Number
MC68HC11E1CFNE3R
Description
MCU 8-BIT 512 RAM 3MHZ 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheet

Specifications of MC68HC11E1CFNE3R

Core Processor
HC11
Core Size
8-Bit
Speed
3MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Type
ROMless
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Processor Series
HC11E
Core
HC11
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI, SPI
Maximum Clock Frequency
3 MHz
Number Of Programmable I/os
38
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Program Memory Size
-
Lead Free Status / Rohs Status
 Details

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FE — Framing Error Flag
Bit 0 — Unimplemented
7.7.5 Baud Rate Register
Use this register to select different baud rates for the SCI system. The SCP[1:0] (SCP[2:0] in
MC68HC(7)11E20) bits function as a prescaler for the SCR[2:0] bits. Together, these five bits provide
multiple baud rate combinations for a given crystal frequency. Normally, this register is written once during
initialization. The prescaler is set to its fastest rate by default out of reset and can be changed at any time.
Refer to
TCLR — Clear Baud Rate Counter Bit (Test)
SCP[2:0] — SCI Baud Rate Prescaler Select Bits
RCKB — SCI Baud Rate Clock Check Bit (Test)
Freescale Semiconductor
FE is set when a 0 is detected where a stop bit was expected. Clear the FE flag by reading SCSR with
FE set and then reading SCDR.
Always reads 0
See
0 = Stop bit detected
1 = Zero detected
Table
Table 7-1
7-1.
Address:
SCP2 applies to MC68HC(7)11E20 only. When SCP2 = 1, SCP[1:0] must
equal 0s. Any other values for SCP[1:0] are not decoded in the prescaler
and the results are unpredictable. Refer to
Reset:
Read:
Write:
for normal baud rate selections.
U = Unaffected
$102B
TCLR
Bit 7
0
Figure 7-7. Baud Rate Register (BAUD)
SCP2
6
0
M68HC11E Family Data Sheet, Rev. 5.1
SCP1
5
0
NOTE
SCP0
4
0
Figure 7-8
RCKB
3
0
SCR2
and
U
2
Figure
SCR1
U
1
7-9.
SCR0
Bit 0
U
SCI Registers
113

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