MC68HC11E1CFNE3R Freescale Semiconductor, MC68HC11E1CFNE3R Datasheet - Page 135

• Manufacturer Part Number: MC68HC11E1CFNE3R
• Description: MCU 8-BIT 512 RAM 3MHZ 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC11E1CFNE3R

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Type: ROMless
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Processor Series: HC11E
• Core: HC11
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 3 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

9.4.2 Timer Compare Force Register
The CFORC register allows forced early compares. FOC[1:5] correspond to the five output compares.
These bits are set for each output compare that is to be forced. The action taken as a result of a forced
compare is the same as if there were a match between the OCx register and the free-running counter,
except that the corresponding interrupt status flag bits are not set. The forced channels trigger their
programmed pin actions to occur at the next timer count transition after the write to CFORC.
The CFORC bits should not be used on an output compare function that is programmed to toggle its
output on a successful compare because a normal compare that occurs immediately before or after the
force can result in an undesirable operation.
Freescale Semiconductor
Register name: Timer Output Compare 3 Register (High)
Register name: Timer Output Compare 3 Register (Low)
Register name: Timer Output Compare 4 Register (High)
Register name: Timer Output Compare 4 Register (Low)
Address:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
Figure 9-10. Timer Output Compare 3 Register Pair (TOC3)
Figure 9-11. Timer Output Compare 4 Register Pair (TOC4)
$100B
Bit 15
Bit 15
FOC1
Figure 9-12. Timer Compare Force Register (CFORC)
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
1
1
1
1
0
= Unimplemented
FOC2
Bit 14
Bit 14
Bit 6
Bit 6
1
1
1
1
6
6
6
6
6
0
M68HC11E Family Data Sheet, Rev. 5.1
FOC3
Bit 13
Bit 13
Bit 5
Bit 5
5
1
5
1
5
1
5
1
5
0
FOC4
Bit 12
Bit 12
Bit 4
Bit 4
4
1
4
1
4
1
4
1
4
0
Address: $101B
Address: $101D
Address: $101A
Address: $101C
FOC5
Bit 11
Bit 11
Bit 3
Bit 3
3
1
3
1
3
1
3
1
3
0
Bit 10
Bit 10
Bit 2
Bit 2
2
1
2
1
2
1
2
1
2
0
Bit 9
Bit 1
Bit 9
Bit 1
1
1
1
1
1
1
1
1
1
0
Bit 0
Bit 8
Bit 0
Bit 0
Bit 0
Bit 8
Bit 0
Bit 0
Bit 0
1
1
1
1
0
Output Compare
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