MC68HC11E1CFNE3R Freescale Semiconductor, MC68HC11E1CFNE3R Datasheet - Page 41

• Manufacturer Part Number: MC68HC11E1CFNE3R
• Description: MCU 8-BIT 512 RAM 3MHZ 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC11E1CFNE3R

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Type: ROMless
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Processor Series: HC11E
• Core: HC11
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 3 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

A normal mode is selected when MODB is logic 1 during reset. One of three reset vectors is fetched from
address $FFFA–$FFFF, and program execution begins from the address indicated by this vector. If
MODB is logic 0 during reset, the special mode reset vector is fetched from addresses $BFFA–$BFFF,
and software has access to special test features. Refer to
RBOOT — Read Bootstrap ROM Bit
SMOD and MDA — Special Mode Select and Mode Select A Bits
Freescale Semiconductor
Valid only when SMOD is set (bootstrap or special test mode); can be written only in special modes
The initial value of SMOD is the inverse of the logic level present on the MODB pin at the rising edge
of reset. The initial value of MDA equals the logic level present on the MODA pin at the rising edge of
reset. These two bits can be read at any time. They can be written anytime in special modes. MDA can
be written only once in normal modes. SMOD cannot be set once it has been cleared.
0 = Bootloader ROM disabled and not in map
1 = Bootloader ROM enabled and in map at $BE00–$BFFF
Resets:
1. The reset values depend on the mode selected at the RESET pin rising edge.
Single chip:
Expanded:
Bootstrap:
MODB
Read:
Write:
Test:
1
1
0
0
Figure 2-9. Highest Priority I-Bit Interrupt and Miscellaneous
Input Levels
at Reset
RBOOT
Bit 7
MODB
0
0
1
0
Address:
1
1
(1)
MODA
Table 2-1. Hardware Mode Select Summary
Input
0
1
0
1
SMOD
MODA
6
0
0
1
1
$103C
M68HC11E Family Data Sheet, Rev. 5.1
0
1
(1)
Special test
MDA
Single chip
Expanded
Bootstrap
Register (HPRIO)
5
0
1
0
1
Mode
(1)
Single chip
Expanded
IRV(NE)
Mode
4
0
0
0
1
(1)
RBOOT
Chapter 5 Resets and
PSEL3
0
0
1
0
3
0
0
0
0
Control Bits in HPRIO
(Latched at Reset)
Latched at Reset
SMOD
0
0
PSEL2
SMOD
2
1
1
1
1
0
0
1
1
MDA
0
1
PSEL1
1
1
1
1
1
Interrupts.
MDA
0
1
0
1
PSEL0
Bit 0
0
0
0
0
Memory Map
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