MC68HC11E1CFNE3R Freescale Semiconductor, MC68HC11E1CFNE3R Datasheet - Page 63

• Manufacturer Part Number: MC68HC11E1CFNE3R
• Description: MCU 8-BIT 512 RAM 3MHZ 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC11E1CFNE3R

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Type: ROMless
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Processor Series: HC11E
• Core: HC11
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 3 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

MULT — Multiple Channel/Single Channel Control Bit
CD:CA — Channel Selects D:A Bits
Freescale Semiconductor
When this control bit is clear, the four requested conversions are performed once to fill the four result
registers. When this control bit is set, conversions are performed continuously with the result registers
updated as data becomes available.
When this bit is clear, the A/D converter system is configured to perform four consecutive conversions
on the single channel specified by the four channel select bits CD:CA (bits [3:0] of the ADCTL register).
When this bit is set, the A/D system is configured to perform a conversion on each of four channels
where each result register corresponds to one channel.
Refer to
channel select bits (CB and CA) have no meaning and the CD and CC bits specify which group of four
channels is to be converted.
Table
When the multiple-channel continuous scan mode is used, extra care is
needed in the design of circuitry driving the A/D inputs. The charge on the
capacitive DAC array before the sample time is related to the voltage on the
previously converted channel. A charge share situation exists between the
internal DAC capacitance and the external circuit capacitance. Although
the amount of charge involved is small, the rate at which it is repeated is
every 64 µs for an E clock of 2 MHz. The RC charging rate of the external
circuit must be balanced against this charge sharing effect to avoid errors
in accuracy. Refer to M68HC11 Reference Manual, Freescale document
order number M68HC11RM/AD, for further information.
3-2. When a multiple channel mode is selected (MULT = 1), the two least significant
Channel Select
1. Used for factory testing
CD:CC:CB:CA
Control Bits
Table 3-2. A/D Converter Channel Selection
10XX
0000
0001
0010
0011
0100
0101
0110
0111
1100
1101
1110
1111
M68HC11E Family Data Sheet, Rev. 5.1
Channel Signal
Reserved
Reserved
(V
V
V
RH
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
NOTE
RH
RL
)/2
(1)
(1)
(1)
(1)
Result in ADRx
if MULT = 1
ADR1
ADR2
ADR3
ADR4
ADR1
ADR2
ADR3
ADR4
ADR1
ADR2
ADR3
ADR4
—
A/D Control/Status Register
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