MC68HC11E1CFNE3R Freescale Semiconductor, MC68HC11E1CFNE3R Datasheet - Page 82

MCU 8-BIT 512 RAM 3MHZ 52-PLCC

MC68HC11E1CFNE3R

Manufacturer Part Number
MC68HC11E1CFNE3R
Description
MCU 8-BIT 512 RAM 3MHZ 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheet

Specifications of MC68HC11E1CFNE3R

Core Processor
HC11
Core Size
8-Bit
Speed
3MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Type
ROMless
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Processor Series
HC11E
Core
HC11
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI, SPI
Maximum Clock Frequency
3 MHz
Number Of Programmable I/os
38
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Program Memory Size
-
Lead Free Status / Rohs Status
 Details

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Resets and Interrupts
5.2.5 System Configuration Options Register
ADPU — Analog-to-Digital Converter Power-Up Bit
CSEL — Clock Select Bit
IRQE — Configure IRQ for Edge-Sensitive-Only Operation Bit
DLY — Enable Oscillator Startup Delay Bit
CME — Clock Monitor Enable Bit
Bit 2 — Unimplemented
CR[1:0] — COP Timer Rate Select Bit
82
Refer to
Refer to
Refer to
Converter.
This control bit can be read or written at any time and controls whether or not the internal clock monitor
circuit triggers a reset sequence when the system clock is slow or absent. When it is clear, the clock
monitor circuit is disabled, and when it is set, the clock monitor circuit is enabled. Reset clears the CME
bit.
Always reads 0
The internal E clock is first divided by 2
bits determine a scaling factor for the watchdog timer. See
0 = IRQ is configured for level-sensitive operation.
1 = IRQ is configured for edge-sensitive-only operation.
0 = Clock monitor circuit disabled
1 = Slow or stopped clocks cause reset
Chapter 3 Analog-to-Digital (A/D)
Chapter 3 Analog-to-Digital (A/D)
Chapter 2 Operating Modes and On-Chip Memory
1. Can be written only once in first 64 cycles out of reset in normal mode or at any time in special modes
Address:
Reset:
Read:
Write:
Figure 5-2. System Configuration Options Register (OPTION)
$1039
ADPU
Bit 7
0
= Unimplemented
CSEL
0
6
M68HC11E Family Data Sheet, Rev. 5.1
IRQE
15
5
0
(1)
before it enters the COP watchdog system. These control
Converter.
Converter.
DLY
4
1
(1)
CME
3
0
Table 5-1
and
Chapter 3 Analog-to-Digital (A/D)
2
0
for specific timeout settings.
CR1
1
0
(1)
Freescale Semiconductor
CR0
Bit 0
0
(1)

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