MC68HC711D3CFNE3 Freescale Semiconductor, MC68HC711D3CFNE3 Datasheet - Page 24

IC MCU 8BIT 2MHZ 44-PLCC

MC68HC711D3CFNE3

Manufacturer Part Number
MC68HC711D3CFNE3
Description
IC MCU 8BIT 2MHZ 44-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheets

Specifications of MC68HC711D3CFNE3

Core Processor
HC11
Core Size
8-Bit
Speed
3MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
26
Program Memory Size
4KB (4K x 8)
Program Memory Type
OTP
Ram Size
192 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-PLCC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-

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3.1.5 Program Counter (PC)
3.1.6 Condition Code Register (CCR)
3.1.6.1 Carry/Borrow (C)
3-4
When a subroutine is called by a jump to subroutine (JSR) or branch to subroutine
(BSR) instruction, the address of the instruction after the JSR or BSR is automatically
pushed onto the stack, least significant byte first. When the subroutine is finished, a
return from subroutine (RTS) instruction is executed. The RTS pulls the previously
stacked return address from the stack, and loads it into the program counter. Execu-
tion then continues at this recovered return address.
When an interrupt is recognized, the current instruction finishes normally, the return
address (the current value in the program counter) is pushed onto the stack, all of the
CPU registers are pushed onto the stack, and execution continues at the address
specified by the vector for the interrupt. At the end of the interrupt service routine, an
RTI instruction is executed. The RTI instruction causes the saved registers to be pulled
off the stack in reverse order. Program execution resumes at the return address.
There are instructions that push and pull the A and B accumulators and the X and Y
index registers. These instructions are often used to preserve program context. For ex-
ample, pushing accumulator A onto the stack when entering a subroutine that uses ac-
cumulator A, and then pulling accumulator A off the stack just before leaving the
subroutine, ensures that the contents of a register will be the same after returning from
the subroutine as it was before starting the subroutine.
The program counter, a 16-bit register, contains the address of the next instruction to
be executed. After reset, the program counter is initialized from one of six possible
vectors, depending on operating mode and the cause of reset.
This 8-bit register contains five condition code indicators (C, V, Z, N, and H), two inter-
rupt masking bits, (IRQ and XIRQ) and a stop disable bit (S). In the M68HC11 CPU,
condition codes are automatically updated by most instructions. For example, load ac-
cumulator A (LDAA) and store accumulator A (STAA) instructions automatically set or
clear the N, Z, and V condition code flags. Pushes, pulls, add B to X (ABX), add B to
Y (ABY), and transfer/exchange instructions do not affect the condition codes. Refer
to Table 3-2, which shows what condition codes are affected by a particular instruc-
tion.
The C bit is set if the arithmetic logic unit (ALU) performs a carry or borrow during an
arithmetic operation. The C bit also acts as an error flag for multiply and divide opera-
Test or Boot
Normal
Freescale Semiconductor, Inc.
Table 3-1 Reset Vector Comparison
For More Information On This Product,
POR or Pin
$FFFE, F
$BFFE, F
CENTRAL PROCESSING UNIT
Go to: www.freescale.com
Clock Monitor
$BFFC, D
$FFFC, D
COP Watchdog
TECHNICAL DATA
$FFFA, B
$BFFA, B

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