MC68HC705C9ACFBE Freescale Semiconductor, MC68HC705C9ACFBE Datasheet - Page 17

• Manufacturer Part Number: MC68HC705C9ACFBE
• Description: IC MCU 8BIT 44-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of MC68HC705C9ACFBE

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 2.1MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 24
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: OTP
• Ram Size: 352 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFP
• Processor Series: HC705C
• Core: HC05
• Data Bus Width: 8 bit
• Data Ram Size: 352 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 2.1 MHz
• Number Of Programmable I/os: 31
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Package: 44PQFP
• Family Name: HC05
• Maximum Speed: 2.1 MHz
• Operating Supply Voltage: 3.3|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

C12A — C12A/C9A Mode Select Bit
C12IRQ — C12A Interrupt Request Bit
STOPDIS — STOP Instruction Disable Bit
C12COPE — C12A COP Enable Bit
SEC — Security Enable Bit
Freescale Semiconductor
This read/write bit selects between C12A configuration and C9A configuration.
This read/write bit selects between an edge-triggered only or edge- and level-triggered external
interrupt pin. If configured in C9A mode, this bit has no effect and will be forced to 0 regardless of the
programmed state.
This read-only bit allows emulation of the “STOP disable” mask option on the MC68HC05C12A. (See
5.9 COP During Stop
forced to 0 regardless of the programmed state.
This read-only bit enables the COP function when configured in MC68HC05C12A mode. If configured
in MC68HC05C9A mode, this bit has no effect and will be forced to 0 regardless of the programmed
state.
This read-only bit enables the EPROM security feature. Once programmed, this bit helps to prevent
external access to the programmed EPROM data. The EPROM data cannot be verified or modified.
1 = Configured to emulate MC68HC05C12A
0 = Configured to emulate MC68HC05C9A
1 = Edge and level interrupt option selected
0 = Edge-only interrupt option selected
1 = If the MCU enters stop mode, the clock monitor is enabled to force a system reset
0 = STOP instruction executed as normal
1 = When in C12A mode, this enables the C12ACOP watchdog timer.
0 = When in C12A mode, this disables the C12ACOP watchdog timer.
1 = Security enabled
0 = Security disabled
Any Port B pin configured for interrupt capability will follow the same edge
or edge/level trigger as the IRQ pin.
During power-on reset, the device always will be configured as
MC68HC05C9A regardless of the state of the C12A bit.
$3FF1
Read:
Write:
Bit 7
SEC
Mode.) If configured in MC68HC05C9A mode, this bit has no effect and will be
MC68HC05C9A Advance Information Data Sheet, Rev. 4.1
= Unimplemented
Figure 1-3. Mask Option Register 2
6
5
NOTE
NOTE
4
C12COPE
3
STOPDIS
2
C12IRQ
1
C12A
Bit 0
Mask Options
17