MC68HC705C9ACFBE Freescale Semiconductor, MC68HC705C9ACFBE Datasheet - Page 56

• Manufacturer Part Number: MC68HC705C9ACFBE
• Description: IC MCU 8BIT 44-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of MC68HC705C9ACFBE

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 2.1MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 24
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: OTP
• Ram Size: 352 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFP
• Processor Series: HC705C
• Core: HC05
• Data Bus Width: 8 bit
• Data Ram Size: 352 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 2.1 MHz
• Number Of Programmable I/os: 31
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Package: 44PQFP
• Family Name: HC05
• Maximum Speed: 2.1 MHz
• Operating Supply Voltage: 3.3|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Capture/Compare Timer
8.3.5 Input Capture Registers
When a selected edge occurs on the TCAP pin, the current high and low bytes of the 16-bit counter are
latched into the input capture registers (ICRH and ICRL). Reading ICRH before reading ICRL inhibits
further capture until ICRL is read. Reading ICRL after reading the status register clears the input capture
flag (ICF). Writing to the input capture registers has no effect.
8.3.6 Output Compare Registers
When the value of the 16-bit counter matches the value in the output compare registers (OCRH and
OCRL), the planned TCMP pin action takes place. Writing to OCRH before writing to OCRL inhibits timer
compares until OCRL is written. Reading or writing to OCRL after the timer status register clears the
output compare flag (OCF).
56
To prevent interrupts from occurring between readings of ICRH and ICRL,
set the interrupt flag in the condition code register before reading ICRH, and
clear the flag after reading ICRL.
OCRH
Reset:
Reset:
Reset:
Reset:
$0014
$0015
$0016
OCRL
$0017
Read:
Write:
Read:
Write:
Write:
Read:
Read:
Write:
ICRH
ICRL
Figure 8-7. Output Compare Registers (OCRH and OCRL)
Bit 15
Bit 15
Bit 7
Bit 7
Bit 7
Figure 8-6. Input Capture Registers (ICRH and ICRL)
Bit 7
Bit 7
Bit 7
MC68HC05C9A Advance Information Data Sheet, Rev. 4.1
= Unimplemented
Bit 14
Bit 14
Bit 6
Bit 6
6
6
6
6
Bit 13
Bit 13
Bit 5
Bit 5
5
5
5
5
NOTE
Unaffected by reset
Unaffected by reset
Unaffected by reset
Unaffected by reset
Bit 12
Bit 12
Bit 4
Bit 4
4
4
4
4
Bit 11
Bit 11
Bit 3
Bit 3
3
3
3
3
Bit 10
Bit 10
Bit 2
Bit 2
2
2
2
2
Bit 9
Bit 1
Bit 9
Bit 1
1
1
1
1
Freescale Semiconductor
Bit 0
Bit 8
Bit 0
Bit 0
Bit 0
Bit 8
Bit 0
Bit 0