MC68HC705C9ACFBE Freescale Semiconductor, MC68HC705C9ACFBE Datasheet - Page 57

IC MCU 8BIT 44-QFP

MC68HC705C9ACFBE

Manufacturer Part Number
MC68HC705C9ACFBE
Description
IC MCU 8BIT 44-QFP
Manufacturer
Freescale Semiconductor
Series
HC05r
Datasheet

Specifications of MC68HC705C9ACFBE

Core Processor
HC05
Core Size
8-Bit
Speed
2.1MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
24
Program Memory Size
16KB (16K x 8)
Program Memory Type
OTP
Ram Size
352 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFP
Processor Series
HC705C
Core
HC05
Data Bus Width
8 bit
Data Ram Size
352 B
Interface Type
SCI, SPI
Maximum Clock Frequency
2.1 MHz
Number Of Programmable I/os
31
Number Of Timers
1
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit
Package
44PQFP
Family Name
HC05
Maximum Speed
2.1 MHz
Operating Supply Voltage
3.3|5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
 Details

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To prevent OCF from being set between the time it is read and the time the output compare registers are
updated, use this procedure:
8.4 Timer During Wait Mode
The CPU clock halts during the wait mode, but the timer remains active. If interrupts are enabled, a timer
interrupt will cause the processor to exit the wait mode.
8.5 Timer During Stop Mode
In the stop mode, the timer stops counting and holds the last count value if STOP is exited by an interrupt.
If STOP is exited by reset, the counters are forced to $FFFC. During STOP, if at least one valid input
capture edge occurs at the TCAP pins, the input capture detect circuit is armed. This does not set any
timer flags or wake up the MCU, but if an interrupt is used to exit stop mode, there is an active input
capture flag and data from the first valid edge that occurred during the stop mode. If reset is used to exit
stop mode, then no input capture flag or data remains, even if a valid input capture edge occurred.
Freescale Semiconductor
1. Disable interrupts by setting the I bit in the condition code register.
2. Write to OCRH. Compares are now inhibited until OCRL is written.
3. Clear bit OCF by reading timer status register (TSR).
4. Enable the output compare function by writing to OCRL.
5. Enable interrupts by clearing the I bit in the condition code register.
MC68HC05C9A Advance Information Data Sheet, Rev. 4.1
Timer During Wait Mode
57

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